A42U2604V-60 データシートの表示（PDF） - AMIC Technology
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A42U2604V-60 Datasheet PDF : 25 Pages
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Selection Guide
Symbol
tRAC
tAA
tCAC
tOEA
tRC
tPC
Description
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
Functional Description
The A42U2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 4 common I/O pins, with RAS , CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A42U2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (tcp). Since data can be output after CAS goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
A42U2604 Series
-50
-60
-80
Unit
50
60
80
ns
22
27
37
ns
13
15
20
ns
13
15
20
ns
84
100
132
ns
20
24
32
ns
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
PRELIMINARY (June, 2002, Version 0.3)
2
AMIC Technology, Inc.
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