SST29EE512 データシートの表示（PDF） - Silicon Storage Technology
部品番号
コンポーネント説明
メーカー
SST29EE512 Datasheet PDF : 26 Pages
| |||
512 Kbit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
Data Sheet
A11
1
A9
2
A8
3
A13
4
A14
5
NC
6
WE#
7
VDD
8
NC
9
NC
10
A15
11
A12
12
A7
13
A6
14
A5
15
A4
16
Standard Pinout
Top View
Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP
32
OE#
31
A10
30
CE#
29
DQ7
28
DQ6
27
DQ5
26
DQ4
25
DQ3
24
VSS
23
DQ2
22
DQ1
21
DQ0
20
A0
19
A1
18
A2
17
A3
301 ILL F01.2
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6 32-pin 27
7 PDIP 26
8 Top View 25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
301 ILL F02.2
FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
A15-A7
A6-A0
DQ7-DQ0
Pin Name
Row Address Inputs
Column Address Inputs
Data Input/output
CE#
OE#
WE#
VDD
Chip Enable
Output Enable
Write Enable
Power Supply
VSS
Ground
NC
No Connection
Functions
To provide memory addresses. Row addresses define a page for a Write cycle.
Column Addresses are toggled to load page data
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide: 5.0V supply (±10%) for SST29EE512
3.0V supply (3.0-3.6V) for SST29LE512
2.7V supply (2.7-3.6V) for SST29VE512
Unconnected pins.
T2.1 301
©2001 Silicon Storage Technology, Inc.
5
S71060-06-000 6/01 301
Share Link: 