LH543621P-35 データシートの表示（PDF） - Sharp Electronics
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LH543621P-35 Datasheet PDF : 57 Pages
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512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
OPERATIONAL DESCRIPTION
Reset
The device is reset whenever the asynchronous Reset
(RS) input is taken LOW, and at least one rising edge and
one falling edge of both CKA and CKB occur while RS is
LOW. A reset operation is required after power-up, before
the first write operation may occur. The LH543611/21 is
fully ready for operation after being reset. No device
programming is required if the default states described
below are acceptable.
A reset operation initializes the read-address and
write-address pointers for FIFO #1 and FIFO #2 to those
FIFO’s first physical memory locations. If the respective
outputs are enabled, the initial contents of these first
locations appear at the outputs. FIFO and mailbox status
flags are updated to indicate an empty condition. In
addition, the programmable-status-flag offset values are
initialized to eight. Thus, the AE1/AE2 flags get asserted
within eight locations of an empty condition, and the
AF1/AF2 flags likewise get asserted within eight locations
of a full condition, for FIFO #1/FIFO #2 respectively.
Bypass Operation
During reset (whenever RS is LOW) the device acts
as a registered transceiver, bypassing the internal FIFO
memories. Port A acts as the master port. A write or read
operation on Port A during reset transfers data directly to
or from Port B. Port B is considered to be the slave, and
cannot perform write or read operations independently on
its own during reset.
The direction of the bypass data transmission is deter-
mined by the R/WA control input, which does not get
overridden by the RS input. Here, a ‘write’ operation
means passing data from Port A to Port B, and a ‘read’
operation means passing data from Port B to Port A.
The bypass capability may be used to pass initializa-
tion or configuration data directly between a master proc-
essor and a peripheral device during reset.
Address Modes
Address pins select the device resource to be
accessed by each port. Port A has three resource-regis-
ter-select inputs, A0A,A1A, and A2A, which select between
FIFO access, mailbox-register access, control-register
access, and programmable flag-offset-value-register ac-
cess. Port B has a single address input, A0B, to select
between FIFO access or mailbox-register access.
The status of the resource-register-select inputs is
sampled at the rising edge of an enabled clock (CKA or
CKB). Resource-register select-input address definitions
are summarized in Table 1.
Table 1. Resource-Register Addresses
A2A A1A A0A
HHH
HHL
HLH
HLL
LHH
LHL
LLH
LLL
A0B
H
L
RESOURCE
PORT A
FIFO
Mailbox
AF2, AE2, AF1, AE1 Flag Offsets
Register (36-Bit Mode)
Control Register Flag-
Synchronization and Parity
Operating Mode
AE1 Flag Offset Register
AF1 Flag Offset Register
AE2 Flag Offset Register
AF2 Flag Offset Register
RESOURCE
PORT B
FIFO
Mailbox
Control Register
The eighteen Control-Register bits govern the syn-
chronization mode of the fullness-status flags at each
port, the choice of odd or even parity at both ports, the
enabling of parity generation for data flow at each port,
the optional latching behavior of the parity-error flags at
each port, and the selection of a full-word or half-word or
single-byte field for parity checking. A reset operation
initializes the LH543611/21 Control Register for
LH5420/LH543601-compatible operation, but it may be
reprogrammed at will at any time during LH543611/21
operation.
FIFO Write
Port A writes to FIFO #1, and Port B writes to FIFO #2.
A write operation is initiated on the rising edge of a clock
(CKA or CKB) whenever: the appropriate enable (ENA or
ENB) is held HIGH; the appropriate request (REQA or
REQB) is held HIGH; the appropriate Read/Write control
(R/WA or R/WB) is held LOW; the FIFO address is
selected for the address inputs (A2A – A0A or A0B); and
the prescribed setup times and hold times are observed
for all of these signals. Setup times and hold times must
also be observed on the data-bus pins (D0A – D35A or
D0B – D35B).
Normally, the appropriate Output Enable signal (OEA
or OEB) is HIGH, to disable the outputs at that port, so
that the data word present on the bus from external
sources gets stored. However, a ‘loopback’ mode of
operation also is possible, in which the data word supplied
by the outputs of one internal FIFO is ‘turned around’ at
the port and read back into the other FIFO. In this mode,
the outputs at the port are not disabled. To remain within
specification for all timing parameters, the Clock Cycle
Frequency must be reduced slightly below the value
11
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