LH543611M-25 データシートの表示（PDF） - Sharp Electronics

部品番号

コンポーネント説明

メーカー

LH543611M-25

512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO

Sharp Electronics 

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

Two mailbox registers provide a separate path for

passing control words or status words between ports.

Each mailbox has a New-Mail-Alert Flag, which is syn-

chronized to the reading port’s clock. This mailbox func-

tion facilitates the synchronization of data transfers

between asynchronous systems.

Data-bypass mode allows Port A to directly transfer

data to or from Port B at reset. In this mode, the device

acts as a registered transceiver under the control of

Port A. For instance, a master processor on Port A can

use the data bypass feature to send or receive initializa-

tion or configuration information directly, to or from a

peripheral device on Port B, during system startup.

A word-width-select option is provided on Port B for

36-bit, 18-bit, or 9-bit data access. This feature allows

word-width matching between Port A and Port B, with no

additional logic needed. It also ensures maximum utiliza-

tion of bus band widths. Subject to meeting timing require-

ments, the word-width selection may be changed at any

time during the operation of an LH543611 or LH543621,

without the need either for a reset operation or for passing

dummy words through Port B immediately after the

change; except that if the change is not made at a

full-word boundary, at least one dummy word must be

passed through Port B before any actual data words

are transmitted.

A Byte Parity Check Flag at each port monitors data

integrity. Control-Register bit 00 (zero) selects the parity

mode, odd or even. This bit is initialized for odd data parity

at reset; but it may be reprogrammed for even parity, or

back again to odd parity, as desired. The parity flags may

be programmed to operate either in a latched mode or in

a flowthrough mode. The parity checking may be per-

formed over 36-bit full-words, over 18-bit half-words, or

over 9-bit single bytes.

Parity generation may be selected as well as parity

checking, and may likewise be performed over full-words

or half-words or single bytes. In any case, a parity bit of

the proper mode is generated over the least-significant

eight bits of a byte, and then is stored in the most-signifi-

cant bit position of the byte as it passes through the

LH543611/21, overwriting whatever bit was present in

that bit position previously.

2

Share Link: