LH543611P-25 データシートの表示（PDF） - Sharp Electronics

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LH543611P-25

512 × 36 × 2 / 1024 × 36 × 2 Synchronous Bidirectional FIFO

Sharp Electronics 

LH543611/21

512 x 36 x 2/1024 x 36 x 2 BiFIFOs

WRITE

PORT A

I/O

READ

FIFO 1

FIFO 2

READ

PORT B

I/O

WRITE

PORT A

CONTROL

PORT B

CONTROL

Figure 3a. Simplified LH543611/21 Block Diagram

543611-3

FR1

RS

MBF2

A2A

A1A

A0A

CKA

R/WA

ENA

REQA

ACKA

FF1

AF1

HF1

RT2

EF2

AE2

RESET

FR2

LOGIC

COMMAND

PORT AND

REGISTER

PORT A

SYNCH-

RONOUS

CONTROL

LOGIC

BYPASS

MAILBOX

REGISTER

#1

MAILBOX

REGISTER

#2

FIFO #1

MEMORY ARRAY

512 x 36 / 1024 x 36

WRITE

POINTER

READ

POINTER

FIXED AND

PROGRAMMABLE

STATUS FLAGS

FIXED AND

PROGRAMMABLE

STATUS FLAGS

MBF1

COMMAND

PORT AND

A0B

REGISTER

PORT B

SYNCH-

RONOUS

CONTROL

LOGIC

CKB

R/WB

ENB

REQB

ACKB

EF1

AE1

RT1

FF2

AF2

HF2

OEA

D0A - D35A

PFA

PORT A

I/O

PARITY

CHECKING

AND

GENERATION

READ

POINTER

WRITE

POINTER

FIFO #2

MEMORY ARRAY

512 x 36 / 1024 x 36

RESOURCE

REGISTERS

PORT B

I/O

PARITY

CHECKING

AND

GENERATION

Figure 3b. Detailed LH543611/21 Block Diagram

OEB

D0B - D35B

WS0, WS1

PFB

543611-4

6

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