M27V320 データシートの表示（PDF） - STMicroelectronics

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M27V320

32 Mbit (4Mb x8 or 2Mb x16) OTP EPROM

STMicroelectronics 

M27V320

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)

Symbol

Parameter

Test Condition

Min

Max

ILI

Input Leakage Current

0V ≤ VIN ≤ VCC

±1

ILO Output Leakage Current

0V ≤ VOUT ≤ VCC

±10

ICC Supply Current

E = VIL, GVPP = VIL, IOUT = 0mA,

f = 5MHz, VCC ≤ 3.6V

30

ICC1 Supply Current (Standby) TTL

E = VIH

1

ICC2 Supply Current (Standby) CMOS

E > VCC – 0.2V, VCC ≤ 3.6V

60

IPP Program Current

VPP = VCC

10

VIL

Input Low Voltage

–0.6 0.2VCC

VIH (2) Input High Voltage

0.7VCC VCC + 0.5

VOL Output Low Voltage

IOL = 2.1mA

0.4

VOH Output High Voltage TTL

IOH = –400µA

2.4

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Maximum DC voltage on Output is VCC +0.5V.

Unit

µA

µA

mA

mA

µA

µA

V

V

V

V

Two Line Output Control

Because EPROMs are usually used in larger

memory arrays, this product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, while GVPP should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

supplies to the devices. The supply current ICC

has three segments of importance to the system

designer: the standby current, the active current

and the transient peaks that are produced by the

falling and rising edges of E.

The magnitude of the transient current peaks is

dependent on the capacitive and inductive loading

of the device outputs. The associated transient

voltage peaks can be suppressed by complying

with the two line output control and by properly se-

lected decoupling capacitors. It is recommended

that a 0.1µF ceramic capacitor is used on every

device between VCC and VSS. This should be a

high frequency type of low inherent inductance

and should be placed as close as possible to the

device. In addition, a 4.7µF electrolytic capacitor

should be used between VCC and VSS for every

eight devices. This capacitor should be mounted

near the power supply connection point. The pur-

pose of this capacitor is to overcome the voltage

drop caused by the inductive effects of PCB trac-

es.

5/15

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