M29F002 データシートの表示（PDF） - STMicroelectronics

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M29F002

2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory

STMicroelectronics 

M29F002T, M29F002NT, M29F002B

Instructions

Seven instructions are defined to perform Read

Array, Auto Select (to read the ElectronicSignature

or Block ProtectionStatus), Program, Block Erase,

Chip Erase, Erase Suspend and Erase Resume.

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase

operations.The Status Register Data Polling, Tog-

gle, Error bits may be read at any time, during

programming or erase, to monitor the progress of

the operation.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

Command Interfacewhich iscommon to all instruc-

tions (see Table 8). The third cycle inputs the

instruction set-up command. Subsequent cycles

output the addressed data, Electronic Signature or

Block Protection Status for Read operations. In

order to give additional data protection,the instruc-

tions for Program and Block or Chip Erase require

further command inputs. For a Programinstruction,

the fourth command cycle inputs the address and

data to be programmed. For an Erase instruction

(Block or Chip), the fourth and fifth cycles input a

further Coded sequence before the Erase confirm

command on the sixth cycle. Erasure of a memory

block may be suspended,in orderto read data from

another block or to program data in another block,

and then resumed.

When power is first applied or if VCC falls below

VLKO, the command interface is reset to Read

Array.

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A17). The address inputs for

the memory array are latched during a write opera-

tion on the falling edge of Chip Enable E or Write

Enable W. When A9 is raised to VID, either a Read

ElectronicSignature Manufactureror Device Code,

Block Protection Status or a Write Block Protection

or Block Unprotection is enabled depending on the

combination of levels on A0, A1, A6, A12 and A15.

Data Input/Outputs (DQ0-DQ7). The input is data

to be programmed in the memory array or a com-

mand to be written to the C.I. Both are latched on

the rising edge of Chip Enable E or Write Enable

W. The output is data from the Memory Array, the

Electronic Signature Manufacturer or Device

codes, the Block Protection Status or the Status

register Data Polling bit DQ7, the Toggle Bits DQ6

and DQ2, the Error bit DQ5 or the Erase Timer bit

DQ3. Outputs are valid when Chip Enable E and

Output Enable G are active. The output is high

impedance when the chip is deselected or the

outputs are disabled and when RPNC is at a Low

level.

Chip Enable (E). The Chip Enable input activates

the memory control logic, input buffers, decoders

and sense amplifiers. E High deselectsthe memory

and reduces the power consumptionto the standby

level. E can also be used to control writing to the

command register and to the memory array, while

W remains at a low level. The Chip Enable must be

forced to VID during the Block Unprotection opera-

tion.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. When G is High the outputs are High

impedance. G must be forced to VID level during

Block Protection and Unprotection operations.

Write Enable (W). This input controls writing to the

Command Registerand Addressand Datalatches.

Reset/Block Temporary Unprotect/No Connect

Input (RPNC). The RPNC (not available for the

M29F002NT) input provides hardware reset and

protected block(s) temporary unprotection func-

tions. In read or write mode, the RPNC pin can be

left open (Not Connected) or held at VIH. Reset of

the memory is acheived by pulling RPNC to VIL for

at least 500ns. When the reset pulse is given, if the

memory is in Read or Standby modes, it will be

available for new operations in 50ns after the rising

edge of RPNC. If the memory is in Erase, Erase

Suspend or Program modes the reset will take

10µs. Ahardware reset duringan Eraseor Program

operation will corrupt the data being programmed

or the sector(s) being erased.

Temporary block unprotection is made by holding

RPNC at VID. In this condition previously protected

blocks can be programmed or erased. The transi-

tion of RPNC from VIH to VID must slower than

500ns. When RPNC is returned from VID to VIH all

blocks temporarily unprotected will be again pro-

tected.

VCC Supply Voltage. The power supply for all

operations (Read, Program and Erase).

VSS Ground. VSS is the reference for all voltage

measurements.

DEVICE OPERATIONS

See Tables 4, 5 and 6.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register or the Block Protection

Status. Both Chip Enable E and Output Enable G

must be low in order to read the output of the

memory.

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