M29W400B データシートの表示（PDF） - STMicroelectronics

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M29W400B

4 Mbit (512Kb x8 or 256Kb x16, Boot Block) Low Voltage Single Supply Flash Memory

STMicroelectronics 

M29W400T, M29W400B

Figure 3. Memory Map and Block Address Table (x8)

7FFFFh

7C000h

7BFFFh

7A000h

79FFFh

78000h

77FFFh

70000h

6FFFFh

60000h

5FFFFh

50000h

4FFFFh

40000h

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

00000h

M29W400T

16K BOOT BLOCK

8K PARAMETER BLOCK

8K PARAMETER BLOCK

32K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

7FFFFh

70000h

6FFFFh

60000h

5FFFFh

50000h

4FFFFh

40000h

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

00000h

M29W400B

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

64K MAIN BLOCK

32K MAIN BLOCK

8K PARAMETER BLOCK

8K PARAMETER BLOCK

16K BOOT BLOCK

AI02090

Organisation

The M29W400 is organised as 512K x8 or 256K

x16 bits selectable by the BYTE signal. When

BYTE is Low the Byte-wide x8 organisation is

selected and the address lines are DQ15A–1 and

A0-A17. The Data Input/Output signal DQ15A–1

acts as address line A–1 which selects the lower or

upper Byte of the memory word for output on

DQ0-DQ7, DQ8-DQ14 remain at High impedance.

When BYTE is High the memory uses the address

inputs A0-A17 and the Data Input/Outputs DQ0-

DQ15. Memory control is provided by Chip Enable

E, Output Enable G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RP tri-level

input provides a hardware reset when pulled Low,

and when held High (at VID) temporarily unprotects

blocks previously protected allowing them to be

programed and erased. Erase and Programopera-

tions are controlled by an internal Program/Erase

Controller (P/E.C.). Status Register data output on

DQ7 provides a Data Polling signal, and DQ6 and

DQ2 provide Toggle signals to indicate the state of

the P/E.C operations. A Ready/Busy RB output

indicates the completion of the internal algorithms.

Memory Blocks

The devices feature asymmetrically blocked archi-

tecture providing system memory integration. Both

M29W400Tand M29W400Bdevices have an array

of 11 blocks, one Boot Block of 16 KBytes or 8

KWords, two Parameter Blocks of 8 KBytes or 4

KWords, one Main Block of 32 KBytes or 16

KWords and seven Main Blocks of 64 KBytes or 32

KWords. The M29W400T has the Boot Block at the

top of the memory address space and the

M29W400B locates the Boot Block starting at the

bottom. The memory maps are showed in Figure

3. Each block can be erased separately, any com-

bination of blocks can be specified for multi-block

erase or the entire chip may be erased. The Erase

operations are managed automatically by the

P/E.C. The block erase operation can be sus-

pended in order to read from or program to any

block not being ersased, and then resumed.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment. All previously protected blocks can be

temporarily unprotected in the application.

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