M36W0R5020B0 データシートの表示（PDF） - STMicroelectronics

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M36W0R5020B0

32 Mbit (2Mb x16, Multiple Bank, Burst) Flash Memory and 4 Mbit SRAM, 1.8V Supply Multi-Chip Package

STMicroelectronics 

M36W0R5020T0, M36W0R5020B0

Table 2. Main Operating modes

Operation

EF GF WF LF RPF WAITF(4) E1S E2S GS WS UBS LBS DQ15-DQ0

Flash Read

VIL VIL VIH VIL(2) VIH

Flash Data Out

Flash Write

Flash Address

Latch

VIL VIH VIL VIL(2) VIH

VIL X VIH VIL VIH

SRAM must be disabled

Flash Data In

Flash Data Out

or Hi-Z (3)

Flash Output

Disable

VIL VIH VIH X VIH

Flash Standby VIH X X X VIH

Hi-Z

Any SRAM mode is allowed

Flash Hi-Z

Flash Hi-Z

Flash Reset

XXX

X VIL

Hi-Z

Flash Hi-Z

SRAM Read

SRAM Write

Flash Memory must be disabled

VIL VIH VIL VIH VIL VIL SRAM data out

VIL VIH X VIL VIL VIL SRAM data in

Output Disable

VIL VIH VIH VIH VIL VIL SRAM Hi-Z

SRAM Standby

Any Flash mode is allowed.

VIH X X X X X

X VIL X X X X

SRAM Hi-Z

SRAM Hi-Z

Note: 1. X = Don't care.

2. LF can be tied to VIH if the valid address has been previously latched.

3. Depends on GF.

4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR032FT/B datasheet for details.

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