M36P0R8070E0 データシートの表示（PDF） - Numonyx -> Micron
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M36P0R8070E0 Datasheet PDF : 22 Pages
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Signal descriptions
M36P0R8070E0
2.5
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However,
the WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details on this signal, please refer to the M69KB128AA datasheet for the PSRAM and to
the M58PR256J datasheet for the Flash memory.
2.6
Flash Chip Enable input (EF)
The Chip Enable input activates the control logic, input buffers, decoders, and sense
amplifiers of the Flash memory. When Chip Enable is Low, VIL, and Reset is High, VIH, the
device is in active mode. When Chip Enable is at VIH the Flash memory are deselected, the
outputs are high impedance and the power consumption is reduced to the standby level.
It is not allowed to have EF at VIL and EP at VIL at the same time. Only one memory
component can be enabled at a time.
2.7
Flash Output Enable inputs (GF)
The Output Enable input controls the data outputs during Flash memory bus read
operations.
2.8
Flash Write Enable (WF)
The Write Enable input controls the bus write operation of the Flash memory command
interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
2.9
Flash Write Protect (WPF)
Write Protect is an input that provides additional hardware protection for each block. When
Write Protect is Low, VIL, lock-down is enabled and the protection status of the locked-down
blocks cannot be changed. When Write Protect is at High, VIH, lock-down is disabled and
the locked-down blocks can be locked or unlocked. (See the lock status table in the
M58PR256J datasheet).
2.10
Flash Reset (RPF)
The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current IDD2. After Reset, all blocks are in the locked state and
the Configuration Register is reset. When Reset is at VIH, the device is in normal operation.
Upon exiting reset mode the device enters asynchronous read mode, but a negative
transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be
tied to VRPH .
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