M36P0R8070E0 データシートの表示（PDF） - Numonyx -> Micron
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M36P0R8070E0 Datasheet PDF : 22 Pages
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M36P0R8070E0
2
Signal descriptions
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A23)
Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.
Address A23 is an input for the Flash memory component only. The address inputs select
the cells in the Flash memory array to access during bus read operations. During bus write
operations they control the commands sent to the command interface of the Flash memory’s
Program/Erase Controller.
In the PSRAM the address inputs select the cells in the memory array to access during bus
read and write operations.
2.2
Data input/output (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
For the PSRAM component, the Upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the
data to or from the upper part of the selected address when Upper Byte Enable (UBP) is
driven Low. The Lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the
lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both
UBP and LBP are disabled, the data inputs/ outputs are high impedance.
2.3
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For more details about the Latch Enable signal, please refer to the datasheets of the
respective memory components: M69KB128AA for the PSRAM and M58PR256J for the
Flash memory.
2.4
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For more details about the Clock signal, please refer to the datasheets of the respective
memory components: M69KB128AA for the PSRAM and M58PR256J for the Flash
memory.
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