M470T6554CZ0-C データシートの表示（PDF） - Samsung
部品番号
コンポーネント説明
メーカー
M470T6554CZ0-C
Samsung
M470T6554CZ0-C Datasheet PDF : 18 Pages
| |||
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 Unbuffered SODIMM Ordering Information
Part Number
Density
Organization
M470T3354CZ3-C(L)E7/E6/D5/CC
256MB
32Mx64
M470T3354CZ0-C(L)E7/E6/D5/CC
256MB
32Mx64
M470T6554CZ3-C(L)E7/E6/D5/CC
512MB
64Mx64
M470T6554CZ0-C(L)E7/E6/D5/CC
512MB
64Mx64
M470T2953CZ3-C(L)E7/E6/D5/CC
1GB
128Mx64
M470T2953CZ0-C(L)E7/E6/D5/CC
1GB
128Mx64
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Component Composition
32Mx16(K4T51163QC)*4
32Mx16(K4T51163QC)*4
32Mx16(K4T51163QC)*8
32Mx16(K4T51163QC)*8
64Mx8(K4T51083QC)*16
64Mx8(K4T51083QC)*16
DDR2 SDRAM
Number of Rank
1
1
2
2
2
2
Height
30mm
30mm
30mm
30mm
30mm
30mm
Features
• Performance range
E7 (DDR2-800)
E6 (DDR2-667)
D5 (DDR2-533)
CC (DDR2-400) Unit
Speed@CL3
400
400
400
400
Mbps
Speed@CL4
533
533
533
400
Mbps
Speed@CL5
800
667
533
-
Mbps
CL-tRCD-tRP
5-5-5
5-5-5
4-4-4
3-3-3
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
64Mx8(512Mb) based Module
32Mx16(512Mb) based Module
Row Address
A0-A13
A0-A12
Column Address
A0-A9
A0-A9
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
Rev. 1.2 Aug. 2005
Share Link: