M48T513Y(2002) データシートの表示（PDF） - STMicroelectronics
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M48T513Y Datasheet PDF : 31 Pages
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M48T513Y, M48T513V
OPERATING MODES
Figure 5, page 5 illustrates the static memory array
and the quartz controlled clock oscillator. The
clock locations contain the century, year, month,
date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year), 30,
and 31 day months are made automatically. The
nine clock bytes (7FFFFh-7FFF9h and 7FFF1h)
are not the actual clock counters, they are memory
locations consisting of BiPORT™ READ/WRITE
memory cells within the static RAM array.
The M48T513Y/V includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
7FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa-
tion. Byte 7FFF0h contains additional flag informa-
tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T513Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCC is out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un-
predictable system operation. As VCC falls, the
control circuitry automatically switches to the bat-
tery, maintaining data and clock operation until
valid power is restored.
Table 6. Operating Modes
Mode
VCC
E
G
Deselect
VIH
X
WRITE
READ
4.5 to 5.5V
or
3.0 to 3.6V
VIL
X
VIL
VIL
READ
VIL
VIH
Deselect
VSO to VPFD (min)(1)
X
X
Deselect
≤ VSO(1)
X
X
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 10, page 16 for details.
W
DQ0-DQ7
X
High Z
VIL
DIN
VIH
DOUT
VIH
High Z
X
High Z
Power
Standby
Active
Active
Active
CMOS Standby
X
High Z Battery Back-up Mode
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