M48T513Y(2002) データシートの表示（PDF） - STMicroelectronics

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M48T513Y
(Rev.:2002)

5.0 or 3.3V, 4 Mbit (512 Kbit x 8) TIMEKEEPER® SRAM

STMicroelectronics 

M48T513Y, M48T513V

READ Mode

The M48T513Y/V is in the READ Mode whenever

W (WRITE Enable) is high and E (Chip Enable) is

low. The unique address specified by the 17 Ad-

dress Inputs defines which one of the 524,272

bytes of data is to be accessed. Valid data will be

available at the Data I/O pins within tAVQV (Ad-

dress Access Time) after the last address input

signal is stable, providing the E and G access

times are also satisfied. If the E and G access

times are not met, valid data will be available after

the latter of the Chip Enable Access Times (tELQV)

or Output Enable Access Time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

ed before tAVQV, the data lines will be driven to an

indeterminate state until tAVQV. If the Address In-

puts are changed while E and G remain active,

output data will remain valid for tAXQX (Output

Data Hold Time) but will go indeterminate until the

next Address Access.

Figure 8. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms

A0-A16

E

G

DQ0-DQ7

tAVAV

VALID

tAVQV

tELQV

tELQX

tGLQV

tGLQX

tAXQX

tEHQZ

tGHQZ

DATA OUT

AI01197

Figure 9. Address Controlled, READ Mode AC Waveforms

tAVAV

A0-A16

VALID

tAXQX

tAVQV

DQ0-DQ7

DATA VALID

DATA VALID

AI02324

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