M48Z512BV(2011) データシートの表示（PDF） - STMicroelectronics
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M48Z512BV Datasheet PDF : 21 Pages
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M48Z512BV
Operating modes
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
Min
Max Unit
tAVAV
WRITE cycle time
85
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH WRITE enable pulse width
65
ns
tELEH
Chip enable low to chip enable high
75
ns
tWHAX WRITE enable high to address transition
5
ns
Obsolete Product(s) - Obsolete Product(s) 2.3
tEHAX
Chip enable high to address transition
15
ns
tDVWH
Input valid to WRITE enable high
35
ns
tDVEH
Input valid to chip enable high
35
ns
tWHDX WRITE enable high to input transition
0
ns
tEHDX
tWLQZ(2)(3)
Chip enable high to input transition
WRITE enable low to output Hi-Z
10
ns
30
ns
tAVWH
Address valid to WRITE enable high
75
ns
tAVEH
Address valid to chip enable high
tWHQX(2)(3) WRITE enable high to output transition
75
ns
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid VCC applied, the M48Z512BV operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect,
WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance,
and all inputs are treated as “don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time tWP, WRITE protection
takes place. When VCC drops below VSO, the control circuit switches power to the internal
energy source which preserves data.
The internal coin cell will maintain data in the M48Z512BV after the initial application of VCC
for an accumulated period of at least 10 years when VCC is less than VSO. As system power
returns and VCC rises above VSO, the battery is disconnected, and the power supply is
switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to
allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
Doc ID 14885 Rev 3
11/21
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