M50FW040(2006) データシートの表示（PDF） - STMicroelectronics

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M50FW040
(Rev.:2006)

4-Mbit (512 Kb x8, uniform block) 3-V supply firmware hub Flash memory

STMicroelectronics 

Signal descriptions

2

Signal descriptions

M50FW040

There are two different bus interfaces available on this part. The active interface is selected

before power-up or during Reset using the Interface Configuration Pin, IC.

The signals for each interface are discussed in the Firmware hub (FWH) signal descriptions

section and the Address/Address multiplexed (A/A Mux) signal descriptions section below.

The supply signals are discussed in the Supply signal descriptions section below.

2.1

2.1.1

2.1.2

2.1.3

2.1.4

Firmware hub (FWH) signal descriptions

For the Firmware Hub (FWH) Interface see <Blue>Figure 1., Logic diagram (FWH

interface), and <Blue>Table 1., Signal names (FWH interface).

Input/Output communications (FWH0-FWH3)

All Input and Output Communication with the memory take place on these pins. Addresses

and Data for Bus Read and Bus Write operations are encoded on these pins.

Input communication frame (FWH4)

The Input Communication Frame (FWH4) signals the start of a bus operation. When Input

Communication Frame is Low, VIL, on the rising edge of the Clock a new bus operation is

initiated. If Input Communication Frame is Low, VIL, during a bus operation then the

operation is aborted. When Input Communication Frame is High, VIH, the current bus

operation is proceeding or the bus is idle.

Identification inputs (ID0-ID3)

The Identification Inputs select the address that the memory responds to. Up to 16

memories can be addressed on a bus. For an address bit to be ‘0’ the pin can be left floating

or driven Low, VIL; an internal pull-down resistor is included with a value of RIL. For an

address bit to be ‘1’ the pin must be driven High, VIH; there will be a leakage current of ILI2

through each pin when pulled to VIH; see <Blue>Table 18.

By convention the boot memory must have address ‘0000’ and all additional memories take

sequential addresses starting from ‘0001’.

General-purpose inputs (FGPI0-FGPI4)

The General Purpose Inputs can be used as digital inputs for the CPU to read. The General

Purpose Inputs Register holds the values on these pins. The pins must have stable data

from before the start of the cycle that reads the General Purpose Input Register until after

the cycle is complete. These pins must not be left to float, they should be driven Low, VIL, or

High, VIH.

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