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M50FW040(2006) データシートの表示(PDF) - STMicroelectronics

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M50FW040 Datasheet PDF : 53 Pages
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M50FW040
1
Summary description
Summary description
The M50FW040 is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V)
supply. For fast erasing in production lines an optional 12V power supply can be used to
reduce the erasing time.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Blocks can be protected individually to prevent
accidental Program or Erase commands from modifying the memory. Program and Erase
commands are written to the Command Interface of the memory. An on-chip Program/Erase
Controller simplifies the process of programming or erasing the memory by taking care of all
of the special operations that are required to update the memory contents. The end of a
program or erase operation can be detected and any error conditions identified. The
command set required to control the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by the memory. The primary interface, the
Firmware Hub (or FWH) Interface, uses Intel’s proprietary FWH protocol. This has been
designed to remove the need for the ISA bus in current PC Chipsets; the M50FW040 acts
as the PC BIOS on the Low Pin Count bus for these PC Chipsets.
The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is
designed to be compatible with current Flash Programmers for production line programming
prior to fitting to a PC Motherboard.
The memory is offered in TSOP32 (8 x 14mm), TSOP40 (10 x 20mm) and PLCC32
packages and it is supplied with all the bits erased (set to ’1’).
In order to meet environmental requirements, ST offers the M50FW040 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST
trademark. ECOPACK specifications are available at: www.st.com.
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