M50LPW041N データシートの表示（PDF） - STMicroelectronics
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M50LPW041N Datasheet PDF : 37 Pages
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Figure 4. TSOP Connections
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
VCC
VPP
RP
NC
NC
A9
A8
A7
A6
A5
A4
NC
IC (VIL)
NC
NC
NC
NC
GPI4
NC
CLK
VCC
VPP
RP
NC
NC
GPI3
GPI2
GPI1
GPI0
WP
TBL
1
40
10
31
M50LPW041
11
30
20
21
VSS
VSS
VCC
VCC
LFRAME W
INIT
G
RFU
RB
RFU
DQ7
RFU
DQ6
RFU
DQ5
RFU
DQ4
VCC
VSS
VSS
LAD3
VCC
VSS
VSS
DQ3
LAD2 DQ2
LAD1 DQ1
LAD0 DQ0
ID0
A0
ID1
A1
ID2
A2
ID3
A3
M50LPW041
AI06872
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW041 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in a PLCC32 or TSOP40
(10mm x 20mm) package and is supplied with all
the bits erased (set to 1).
System Memory Mapping
The LPC address sequence is 32 bits long. The
M50LPW041 responds to addresses mapped to
the top of the 4 GByte memory space, from
FFFF FFFFh. Address bits A31-A24 must be set
to 1. A23 is set to 1 for array access, and to 0 for
register access.
The M50LPW041 also responds to addresses
mapped to the bottom of the 4 GByte memory
space, from 0000 0000h. Address bits A31-A24
must be set to 0. A23 is set to 0 for array access,
and to 1 for register access.
For A22-A19, see Table 2. A18-A0 are for array
addresses.
Table 1. Signal Names (LPC Interface) Memory
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID3
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave
disconnected or set at VIL or VIH.
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Erase Operations
VSS
Ground
NC
Not Connected Internally
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