M50LPW080 データシートの表示（PDF） - STMicroelectronics

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M50LPW080

8 Mbit (1M x8, Uniform Block) 3V Supply Low Pin Count Flash Memory

STMicroelectronics 

M50LPW080

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on

this part. The active interface is selected before

power-up or during Reset using the Interface Con-

figuration Pin, IC.

The signals for each interface are discussed in the

Low Pin Count (LPC) Signal Descriptions section

and the Address/Address Multiplexed (A/A Mux)

Signal Descriptions section below. The supply sig-

nals are discussed in the Supply Signal Descrip-

tions section below.

Low Pin Count (LPC) Signal Descriptions

For the Low Pin Count (LPC) Interface see Figure

2. and Table 1..

Input/Output Communications (LAD0-LAD3).

All Input and Output Communication with the

memory take place on these pins. Addresses and

Data for Bus Read and Bus Write operations are

encoded on these pins.

Input Communication Frame (LFRAME). The

Input Communication Frame (LFRAME) signals

the start of a bus operation. When Input Commu-

nication Frame is Low, VIL, on the rising edge of

the Clock a new bus operation is initiated. If Input

Communication Frame is Low, VIL, during a bus

operation then the operation is aborted. When In-

put Communication Frame is High, VIH, the cur-

rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID1). The Identification

Inputs (ID0-ID1) allow to address up to 4 memo-

ries on a bus. The value on addresses A20-A21 is

compared to the hardware strapping on the ID0-

ID1 pins to select which memory is being ad-

dressed. For an address bit to be ‘1’ the corre-

spondent ID pin can be left floating or driven Low,

VIL; an internal pull-down resistor is included with

a value of RIL. For an address bit to be ‘0’ the cor-

respondent ID pin must be driven High, VIH; there

will be a leakage current of ILI2 through each pin

when pulled to VIH (see Table 21.).

By convention the boot memory must have ID0-

ID1 pins left floating or driven Low, VIL and a ‘11’

value on A20-A21 and all additional memories

take sequential ID0-ID1 configuration, as shown in

Table 3..

General Purpose Inputs (GPI0-GPI4). The Gener-

al Purpose Inputs can be used as digital inputs for

the CPU to read. The General Purpose Input Reg-

ister holds the values on these pins. The pins must

have stable data from before the start of the cycle

that reads the General Purpose Input Register un-

til after the cycle is complete. These pins must not

be left to float, they should be driven Low, VIL, or

High, VIH.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the Low Pin Count

(LPC) or the Address/Address Multiplexed (A/A

Mux) Interface is used. The chosen interface must

be selected before power-up or during a Reset

and, thereafter, cannot be changed. The state of

the Interface Configuration, IC, should not be

changed during operation.

To select the Low Pin Count (LPC) Interface the

Interface Configuration pin should be left to float or

driven Low, VIL; to select the Address/Address

Multiplexed (A/A Mux) Interface the pin should be

driven High, VIH. An internal pull-down resistor is

included with a value of RIL; there will be a leakage

current of ILI2 through each pin when pulled to VIH;

see Table 21..

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the memory. When Interface

Reset (RP) is set Low, VIL, the memory is in Reset

mode: the outputs are put to high impedance and

the current consumption is minimized. When RP is

set High, VIH, the memory is in normal operation.

After exiting Reset mode, the memory enters

Read mode.

CPU Reset (INIT). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, LAD0-LAD3. The Clock

conforms to the PCI specification.

Top Block Lock (TBL). The Top Block Lock in-

put is used to prevent the Top Block (Block 15)

from being changed. When Top Block Lock, TBL,

is set Low, VIL, Program and Block Erase opera-

tions in the Top Block have no effect, regardless of

the state of the Lock Register. When Top Block

Lock, TBL, is set High, VIH, the protection of the

Block is determined by the Lock Register. The

state of Top Block Lock, TBL, does not affect the

protection of the Main Blocks (Blocks 0 to 14).

Top Block Lock, TBL, must be set prior to a Pro-

gram or Block Erase operation is initiated and

must not be changed until the operation completes

or unpredictable results may occur. Care should

be taken to avoid unpredictable behavior by

changing TBL during Program or Erase Suspend.

Write Protect (WP). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 14)

from being changed. When Write Protect, WP, is

set Low, VIL, Program and Block Erase operations

in the Main Blocks have no effect, regardless of

the state of the Lock Register. When Write Protect,

WP, is set High, VIH, the protection of the Block is

determined by the Lock Register. The state of

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