M54128L/FP
6. Regarding the IBLI input pin clamping diode
As indicated in the equivalent circuit, seven stages of a series resistance of approx. 2 kΩ and a forward-direction diode
are employed.
(1) The drop in the diode VF at high temperatures may cause the input pin clamping voltage to drop, to approach the
comparator reference potential (2.4 V), so that on the occurrence of a leakage current, the over voltage detection
level may fluctuate somewhat. The detection circuit should be configured as shown below. Also, it is
recommended that R1, R2 and VZ be set as indicated below.
Input
R1
R2
VZ
IBLI pin
• R1 + R2 > 200kΩ
•
R1 x R2
R1 + R2
< 7kΩ
(2) During excessive input, as indicated above, settings should ensure that the input pin voltage is 4.3 V or lower
(to prevent saturation operation of the comparator circuit).
VZ≈4.0 V
7. Regarding the reset time in the reset timer circuit
This circuit is a timer circuit designed for VL = 0.7 V, VH = 2.5 V, and IO = 10 µA; when SCR is turned on, the power
supply to the leakage detection circuit and abnormal voltage detection circuit is interrupted, and VL may not fall to 0.7
V, as shown in the diagram below, so that the reset time is shortened. The reset time should be set to a longer time in
advance.
T = C x (VH - VL) = 0.33µF x (2.4 - 0.7) = 55ms
I
10µA
OFFC pin waveform
2.4V
3.1V
0.7V
55ms
SCRT pin waveform
0V
t = 10 – 20ms
•For leakage detection: times may be shorter by 10 ms (50 Hz)
•For abnormal voltage detection: times may be shorter by 20 ms (50 Hz)
Note: t is the time shorter than the set time
• ln the case of leakage detection :
May become 10ms (50Hz) shorter
• ln the case of abnormal voltage detection :
May become 20ms (50Hz) shorter
Note. t : time shorter than setting value
Rev.1.0, Sep.16.2003, page 11 of 21