M54HC147 データシートの表示（PDF） - STMicroelectronics

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M54HC147

10 TO 4 LINE PRIORITY ENCODER

STMicroelectronics 

M54HC147

M74HC147

10 TO 4 LINE PRIORITY ENCODER

. HIGH SPEED

tPD = 15 ns (TYP.) at VCC = 5 V

. LOW POWER DISSIPATION

ICC = 4 µA (MAX.) at TA = 25 °C

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

. OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

IOH = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V to 6 V

. PIN AND FUNCTION COMPATIBLE

WITH 54/74LS147

DESCRIPTION

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M 54HC 14 7F 1R

M 74H C1 47 M1 R

M 74HC 14 7B 1R

M 74H C1 47 C1 R

The M54/74HC147 is a high speed CMOS 10 TO 4

LINE PRIORITY ENCODER fabricated in silicon

gate C2MOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS low power consumption.

This device features priority encoding of the inputs

to ensure that only the highest order data line is en-

coded. Nine input lines are encoded to a four line

BCD output. The implied decimal zero condition re-

quires no input condition as zero is encoded when

all nine data lines are at high logic level. All data input

and outputs are active at the low logic level. All in-

puts are equipped with protection circuits against

static discharge and transient excess voltage.

PIN CONNECTIONS (top view)

INPUT AND OUTPUT EQUIVALENT CIRCUIT

October 1992

NC =

No Internal

Connection

1/10

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