M58BV016DB7T3F データシートの表示（PDF） - Numonyx -> Micron
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M58BV016DB7T3F Datasheet PDF : 70 Pages
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Signal descriptions
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
2.9
Burst Clock (K)
The Burst Clock, K, is used to synchronize the memory with the external bus during
synchronous burst read operations. Bus signals are latched on the active edge of the Clock.
The Clock can be configured to have an active rising or falling edge. In synchronous burst
read mode the address is latched on the first active clock edge when Latch Enable is Low,
VIL, or on the rising edge of Latch Enable, whichever occurs first.
During asynchronous bus operations the Clock is not used.
2.10
2.11
2.12
2.13
Burst Address Advance (B)
The Burst Address Advance, B, controls the advancing of the address by the internal
address counter during synchronous burst read operations.
Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the
X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address
counter advances. If Burst Address Advance is High, VIH, the internal address counter does
not change; the same data remains on the data inputs/outputs and Burst Address Advance
is not sampled until the Y-latency expires.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R)
The Valid Data Ready output, R, is an open drain output that can be used, during
synchronous burst read operations, to identify if the memory is ready to output data or not.
The Valid Data Ready output can be configured to be active on the clock edge of the invalid
data read cycle or one cycle before. Valid Data Ready, at VIH, indicates that new data is or
will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain
active.
In all asynchronous operations, Valid Data Ready is high impedance. It may be tied to other
components with the same Valid Data Ready signal to create a unique system Ready signal.
The Valid Data Ready output has an internal pull-up resistor of around 1 MΩ powered from
VDDQ, designers should use an external pull-up resistor of the correct value to meet the
external timing requirements for Valid Data Ready going to VIH.
Write Protect (WP)
The Write Protect, WP, provides protection against program or erase operations. When
Write Protect, WP, is at VIL the first two (in the bottom configuration) or last two (in the top
configuration) parameter blocks and all main blocks are locked. When Write Protect WP is
at VIH all the blocks can be programmed or erased, if no other protection is used.
Supply voltage (VDD)
The supply voltage, VDD, is the core power supply. All internal circuits draw their current
from the VDD pin, including the program/erase controller.
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