M58LW064C データシートの表示（PDF） - STMicroelectronics

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M58LW064C

64 Mbit (4Mb x16, Uniform Block, Burst) 3V Supply Flash Memory

STMicroelectronics 

M58LW064C

SUMMARY DESCRIPTION

M58LW064C is a 64 Mbit (4Mb x16) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage (2.7V to 3.6V) core supply.

On power-up the memory defaults to Read mode

with an asynchronous bus where it can be read in

the same way as a non-burst Flash memory.

The memory is divided into 64 blocks of 1Mbit that

can be erased independently so it is possible to

preserve valid data while old data is erased. Pro-

gram and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a Program or Erase operation can be detected and

any error conditions identified in the Status Regis-

ter. The command set required to control the

memory is consistent with JEDEC standards.

The Write Buffer allows the microprocessor to pro-

gram from 1 to 16 Words in parallel, both speeding

up the programming and freeing up the micropro-

cessor to perform other work. A Word Program

command is available to program a single Word.

Erase can be suspended in order to perform either

Read or Program in any other block and then re-

sumed. Program can be suspended to Read data

in any other block and then resumed. Each block

can be programmed and erased over 100,000 cy-

cles.

Individual block protection against Program or

Erase is provided for data security. All blocks are

protected during power-up. The protection of the

blocks is non-volatile; after power-up the protec-

tion status of each block is restored to the state

when power was last removed. Software com-

mands are provided to allow protection of some or

all of the blocks and to cancel all block protection

bits simultaneously. All Program or Erase opera-

tions are blocked when the Program Erase Enable

input VPEN is low.

The Reset/Power-Down pin is used to apply a

Hardware Reset to the memory and to set the de-

vice in power-down mode.

The STS pin gives information about the memory

status. It can be configured in two status: to output

a static signal about the status of P/E C (when low

P/E C is busy, when high P/E C is ready for a new

operation) or to give a pulsing signal to indicate

the end of programming or erasing blocks. In this

last configuration it supplies a system interrupt sig-

nal useful for saving time.

In asynchronous mode Chip Enable, Output En-

able and Write Enable signals control the bus op-

eration of the memory. An Address Latch input can

be used to latch addresses in Latch Controlled

mode. Together they allow simple, yet powerful,

connection to most microprocessors, often without

additional logic.

In synchronous mode all Bus Read operations are

synchronous with the Clock. Chip Enable and Out-

put Enable select the Bus Read operation and the

Latch Enable input is used to latch the address.

The signals are compatible with most micropro-

cessor burst interfaces.

The device includes a 128 bit Protection Register.

The Protection Register is divided into two 64 bit

segments: the first contains a unique device num-

ber written by ST, the second is user programma-

ble. The user programmable segment can be

protected.

The memory is available in TSOP56 (14 x 20 mm)

and TBGA64 (10 x 13mm, 1mm pitch) packages.

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