M58MR016ZC-T データシートの表示（PDF） - STMicroelectronics
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M58MR016ZC-T Datasheet PDF : 51 Pages
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M58MR016C, M58MR016D
The architecture includes a 128 bit Protection reg-
ister that is divided into two 64 bit segments. In the
first one is written a unique device number, while
the second one is programmable by the user. The
user programmable segment can be permanently
protected programming the bit 1 of the Protection
Lock Register (see protection register and Securi-
ty Block). The parameter block (# 0) is a security
block. It can be permanently protected by the user
Table 3. Bank Size and Sectorization
Bank Size
Bank A
4 Mbit
Bank B
12 Mbit
programming the bit 2 of the Protection Lock Reg-
ister.
Block protection against Program or Erase pro-
vides additional data security. All blocks are pro-
tected and unlocked at Power-up. Instructions are
provided to protect or un-protect any block in the
application. A second register locks the protection
status while WP is low (see Block Locking descrip-
tion).
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
7 blocks of 32 KWord
24 blocks of 32 KWord
Figure 3. Memory Map
Bank B
Top Boot Block
Address lines A19-A0
000000h
007FFFh
512 Kbit or
32 KWord
0B8000h
0BFFFFh
0C0000h
0C7FFFh
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Bank A
0F0000h
0F7FFFh
0F8000h
0F8FFFh
512 Kbit or
32 KWord
64 Kbit or
4 KWord
0FF000h
0FFFFFh
64 Kbit or
4 KWord
Total of 24
Main Blocks
Bottom Boot Block
Address lines A19-A0
000000h
000FFFh
64 Kbit or
4 KWord
Bank A
Total of 7
Main Blocks
007000h
007FFFh
008000h
00FFFFh
64 Kbit or
4 KWord
512 Kbit or
32 KWord
Total of 8
Parameter
Blocks
Bank B
038000h
03FFFFh
040000h
047FFFh
0F8000h
0FFFFFh
512 Kbit or
32 KWord
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Total of 8
Parameter
Blocks
Total of 7
Main Blocks
Total of 24
Main Blocks
AI05230
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