M58MR064-ZC データシートの表示（PDF） - STMicroelectronics
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M58MR064-ZC Datasheet PDF : 52 Pages
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M58MR064C, M58MR064D
The architecture includes a 128 bits Protection
register that is divided into two 64-bits segments.
In the first one is written a unique device number,
while the second one is programmable by the us-
er. The user programmable segment can be per-
manently protected programming the bit 1 of the
Protection Lock Register (see protection register
and Security Block). The parameter block (# 0) is
a security block. It can be permanently protected
Table 3. Bank Size and Sectorization
Bank Size
Bank A
16 Mbit
Bank B
48 Mbit
by the user programming the bit 2 of the Protection
Lock Register.
Block protection against Program or Erase pro-
vides additional data security. All blocks are pro-
tected and unlocked at Power-up. Instructions are
provided to protect or un-protect any block in the
application. A second register locks the protection
status while WP is low (see Block Locking descrip-
tion).
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
31 blocks of 32 KWord
96 blocks of 32 KWord
Figure 3. Memory Map
Top Boot Block
Address lines A21-A0
000000h
007FFFh
512 Kbit or
32 KWord
Bank B
2F8000h
2FFFFFh
300000h
307FFFh
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Bank A
3F0000h
3F7FFFh
3F8000h
3F8FFFh
512 Kbit or
32 KWord
64 Kbit or
4 KWord
3FF000h
3FFFFFh
64 Kbit or
4 KWord
Total of 96
Main Blocks
Bottom Boot Block
Address lines A21-A0
000000h
000FFFh
64 Kbit or
4 KWord
Bank A
Total of 31
Main Blocks
007000h
007FFFh
008000h
00FFFFh
64 Kbit or
4 KWord
512 Kbit or
32 KWord
Total of 8
Parameter Bank B
Blocks
0F8000h
0FFFFFh
100000h
107FFFh
3F8000h
3FFFFFh
512 Kbit or
32 KWord
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Total of 8
Parameter
Blocks
Total of 31
Main Blocks
Total of 96
Main Blocks
AI90089
4/52
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