M58WR064 データシートの表示（PDF） - STMicroelectronics

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コンポーネント説明

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M58WR064

64 Mbit (4Mb x 16, Multiple Bank, Burst ) 1.8V Supply Flash Memory

STMicroelectronics 

M58WR064T, M58WR064B

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits 4 and 5 are set and the

command aborts. Erase aborts if Reset turns to

VIL. As data integrity cannot be guaranteed when

the Erase operation is aborted, the block must be

erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register mode un-

til a Read Array, Read CFI Query or Read Elec-

tronic Signature command is issued.

During Erase operations the bank containing the

block being erased will only accept the Read Ar-

ray, Read Status Register, Read Electronic Signa-

ture, Read CFI Query and the Program/Erase

Suspend command, all other commands will be ig-

nored. Refer to Dual Operations section for de-

tailed information about simultaneous operations

allowed in banks not being erased. Typical Erase

times are given in Table 14, Program, Erase

Times and Program/Erase Endurance Cycles.

See Appendix C, Figure 22, Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

for using the Block Erase command.

Bank Erase Command

The Bank Erase command can be used to erase a

bank. It sets all the bits within the selected bank to

’1’. All previous data in the bank is lost. The Bank

Erase command will ignore any protected blocks

within the bank. If all blocks in the bank are pro-

tected then the Bank Erase operation will abort

and the data in the bank will not be changed. The

Status Register will not output any error.

Two Bus Write cycles are required to issue the

command.

s The first bus cycle sets up the Bank Erase

command.

s The second latches the bank address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Bank Erase

Confirm (D0h), Status Register bits b4 and b5 are

set and the command aborts. Erase aborts if Re-

set turns to VIL. As data integrity cannot be guar-

anteed when the Erase operation is aborted, the

bank must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register mode un-

til a Read Array, Read CFI Query or Read Elec-

tronic Signature command is issued.

During Bank Erase operations the bank being

erased will only accept the Read Array, Read Sta-

tus Register, Read Electronic Signature and Read

CFI Query command, all other commands will be

ignored. A Bank Erase operation cannot be sus-

pended.

Refer to Dual Operations section for detailed infor-

mation about simultaneous operations allowed in

banks not being erased. Typical Erase times are

given in Table 14, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

Program Command

The memory array can be programmed word-by-

word. Only one Word in one bank can be pro-

grammed at any one time. Two bus write cycles

are required to issue the Program Command.

s The first bus cycle sets up the Program

command.

s The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

After programming has started, read operations in

the bank being programmed output the Status

Register content.

During Program operations the bank being pro-

grammed will only accept the Read Array, Read

Status Register, Read Electronic Signature, Read

CFI Query and the Program/Erase Suspend com-

mand. Refer to Dual Operations section for de-

tailed information about simultaneous operations

allowed in banks not being programmed. Typical

Program times are given in Table 14, Program,

Erase Times and Program/Erase Endurance Cy-

cles.

Programming aborts if Reset goes to VIL. As data

integrity cannot be guaranteed when the program

operation is aborted, the memory location must be

reprogrammed.

See Appendix C, Figure 18, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Block Erase operation. A

Bank Erase operation cannot be suspended.

One bus write cycle is required to issue the Pro-

gram/Erase command. Once the Program/Erase

Controller has paused bits 7, 6 and/ or 2 of the Sta-

tus Register will be set to ‘1’. The command can be

addressed to any bank.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array (cannot read the suspended block),

Read Status Register, Read Electronic Signature

and Read CFI Query commands. Additionally, if

the suspend operation was Erase then the Clear

status Register, Program, Block Lock, Block Lock-

Down or Protection Program commands will also

be accepted. The block being erased may be pro-

14/81

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