M59BW102N データシートの表示（PDF） - STMicroelectronics

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M59BW102N

1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory

STMicroelectronics 

M59BW102

Figure 4. Block Diagram

DQ0-DQ15

A1-A15

A0

G

LOGIC

E

ALE

EVEN COUNTER

OUTPUT BUFFER

ODD COUNTER

MULTIPLEXER

EVEN MATRIX

(16 x 32K)

ODD MATRIX

(16 x 32K)

AI02765

INSTRUCTIONS AND COMMANDS

The Command Interface latches commands writ-

ten to the memory. Instructions are made up from

one or more commands to perform Read Memory

Array, Read Electronic Signature, Program, Chip

Erase. Commands are made of address and data

sequences. The instructions require from 1 to 6 cy-

cles, the first or first three of which are always write

operations used to initiate the instruction. They are

followed by either further write cycles to confirm

the first command or execute the command imme-

diately. Command sequencing must be followed

exactly. Any invalid combination of commands will

reset the device to Read Array. The increased

number of cycles has been chosen to assure max-

imum data security. Instructions are initialised by

two initial Coded cycles which unlock the Com-

mand Interface. In addition, for Erase, instruction

confirmation is again preceded by the two Coded

cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt from any address during Pro-

gram or Erase command execution will automati-

cally output these five Status Register bits. The P/

E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6

and DQ7. Other bits (DQ0, DQ1 and DQ4) are re-

served for future use and should be masked. See

Table 8.

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programming or

after the sixth W pulse for erase. See Figure 11 for

the Data Polling waveforms and Figure 12 for the

Data Polling flowchart. A Valid Address is the ad-

dress being programmed or any address while

erasing the chip.

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

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