'97.3.21
MITSUBISHI LSIs
M5M5V208FP,VP,RV,KV,KR -70L , -85L, -10L , -12L,
-70LL, -85LL, -10LL, -12LL
(4) TIMING DIAGRAMS
Read cycle
A0~17
S1
(Note 3)
S2
(Note 3)
OE
(Note 3)
DQ1~8
W = "H" level
Write cycle (W control mode)
A0~17
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ta (OE)
ten (OE)
ten (S1)
ten (S2)
tCW
tv (A)
tdis (S1)
tdis (S2)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
(Note 3)
S1
S2
OE
W
DQ1~8
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
(Note 3)
(Note 3)
tsu (A)
tw (W)
trec (W)
tdis (OE)
tdis (W)
ten(OE)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
MITSUBISHI
ELECTRIC
5