M7040N データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M7040N

64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE

STMicroelectronics 

M7040N

OPERATION

Command Bus and DQ Bus

CMD[10:0] carries the command and its associat-

ed parameter. DQ[71:0] is used for data transfer to

and from the database entries. These entries com-

prise a data and a mask field that are organized as

data and mask arrays. The DQ Bus carries the

search data (of the data and mask arrays and in-

ternal registers) during the SEARCH command as

well as the address and data during READ and/or

WRITE operations. The DQ Bus can also carry the

address information for the flow-through accesses

to the external SRAMs and/or SSRAMs.

Database Entry (Data Array and Mask Array)

Each database entry comprises a data and a mask

field. The resultant value of the entry is “1,” “0,” or

“X (don’t care),” depending on the value in the data

and mask bits. The on-chip priority encoder se-

lects the first matching entry in the database that

is nearest to location “0.”

Arbitration Logic

When multiple Search Engines are cascaded to

create large databases, the data being searched is

presented to all Search Engines simultaneously in

the cascaded system. If multiple matches occur

within the cascaded devices, arbitration logic on

the Search Engines will enable the winning device

(with a matching entry that is closest to address “0”

of the cascaded database) to drive the SRAM bus.

Pipeline and SRAM Control

Pipeline latency is added to give enough time to a

cascaded system’s arbitration logic to determine

the device that will drive the index of the matching

entry on the SRAM bus. Pipeline logic adds laten-

cy to both the SRAM access cycles and the SSF

and SSV signals to align them to the host ASIC re-

ceiving the associated data.

Full Logic

Bit[0] in each of the 72-bit entries has a special

purpose for the LEARN command (0 = empty, 1 =

full). When all the data entries have bit[0] = 1, the

database asserts the FULL Flag, indicating all the

Search Engines in the depth-cascaded array are

full.

Connection Descriptions

CLOCK MODE (CLK_MODE). This signal allows

the selection of clock input to the CLK1X/CLK2X

pin. If the CLK_MODE pin is low, CLK2X must be

supplied on that pin. PHS_L must also be sup-

plied. If the CLK_MODE pin is high, CLK1X must

be supplied on the CLK2X/CLK1X pin, and the

PHS_L signal is not required. When the

CLK_MODE is high, PHS_L is unused and should

be externally grounded.

Master Clock (CLK2X/CLK1X). Depending on

the CLK_MODE pin, either the CLK2X or the

CLK1X must be supplied. M7040N samples con-

trol and data signals on both the edges of CLK1X

if CLK1X is supplied. M7040N samples all the data

and control pins on the positive edge of CLK2X if

the CLK2X and PHS_L signals are supplied. All

signals are driven out of the device on the rising

edge of CLK1X if CLK1X is supplied, and are driv-

en on the rising edge of CLK2X (when PHS_L is

low) if CLK2X is supplied.

Phase (PHS_L). This signal runs at half the fre-

quency of CLK2X and generates an internal clock

from CLK2X (see Figure 10, page 21).

Test Output (TEST_CO). This is test output and

will stay unconnected in the application of the de-

vice.

Test Input (TEST). This signal should be con-

nected to ground.

Test Input (TEST_FM). This signal should be

connected to ground.

Reset (RST_L). Driving RST_L low initializes the

device to a known state.

Test Input (TEST_PB). This signal should be

connected to ground.

Configuration. When CFG_L is low, M7040N will

operate in backward compatibility mode with

M7010 and M7020. When CFG_L is low, the

CMD[10:9] should be externally grounded. With

CFG_L low, the device will behave identically with

M7010 and M7020, and the new feature added to

M7040N will be disabled.

When CFG_L is high, the additional command

CMD[10:9] can be used and the following addition-

al features will be supported:

1. 16 pairs of Global Masks are supported instead

of eight;

2. Parallel WRITE to the data and mask arrays is

supported (see Parallel WRITE, page 38); and

3. configuring tables of up to three different widths

does not require table identification bits in the

data array, thus saving two bits from each 72-bit

19/159

Share Link: