M7040N データシートの表示（PDF） - STMicroelectronics

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M7040N

64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE

STMicroelectronics 

M7040N

144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices. . . . . . . . . . . 74

Hit/Miss Assumption (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Hardware Diagram for a Table with 31 Devices (Figure 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Hardware Diagram for a Block of Up to Eight Devices (Figure 53.) . . . . . . . . . . . . . . . . . . . . . . . . 77

x144 Table with 31 Devices (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Timing Diagrams for x144 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 40.). . . . . . . . . . . . . 90

Shift of SSF and SSV from SADR (Table 41.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

288-bit SEARCH on Tables Configured as x288 Using a Single M7040N Device . . . . . . . . . . 90

Hardware Diagram for a Table with One Device (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Timing Diagram for 288-bit SEARCH (One Device) (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . 92

x288 Table with One Device (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Latency of SEARCH from Cycles C and D to SRAM Access Cycle (Table 42.) . . . . . . . . . . . . . . . 93

Shift of SSF and SSV from SADR (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

288-bit SEARCH on Tables x288-configured Using Up to Eight M7040N Devices . . . . . . . . . 94

Hit/Miss Assumption (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Hardware Diagram for a Table with Eight Devices (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

x288 Table with Eight Devices (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Timing Diagrams for x288-configured Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . 98

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 45.). . . . . . . . 101

Shift of SSF and SSV from SADR (Table 46.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

288-bit Search on Tables Configured as x288 Using Up to 31 M7040N Devices. . . . . . . . . . 101

Hit/Miss Assumption (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Hardware Diagram for a Table with 31 Devices (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Hardware Diagram for a Block of Up to Eight Devices (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . 104

x288 Table with 31 Devices (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Timing Diagrams for x288 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 48.). . . . . . . . 117

Shift of SSF and SSV from SADR (Table 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

MIXED SEARCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Tables Configured with Different Widths Using an M7040N with CFG_L LOW . . . . . . . . . . . . . . 117

Tables Configured to Different Widths using an M7040N with CFG_L HIGH . . . . . . . . . . . . . . . . 117

Timing Diagram for Mixed SEARCH (One Device) (Figure 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Multi-Width Configurations Example (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Searches with CFG_L Set HIGH (Table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LRAM AND LDEV DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Timing Diagram of LEARN: TLSZ = 00 (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) (Figure 91.). . . . . . . . . . . . . 122

Timing Diagram of LEARN on Device 7: TLSZ = 01 (Figure 92.) . . . . . . . . . . . . . . . . . . . . . . . . . 123

Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction (Table 51.) . . . . . . . . 123

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