M7040N データシートの表示（PDF） - STMicroelectronics

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M7040N

64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE

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M7040N

Table 2. Signal Names

Symbol

Type(1)

Description

Clocks and Reset

CLK_MODE

I Clock Mode

CLK2X_CLK1X

I

Master Clock

PHS_L

I Phase

TEST_CO(2)

I Test Output (ST Use Only)

TEST

I Test Input (ST Use Only)

TEST_FM

I Test Input (ST Use Only)

RST_L

I Reset

TEST_PB(3)

I Test Input (ST Use Only)

CFG_L

I Configuration

Command and DQ Bus

CMD[10:0]

I Command Bus

CMDV

I Command Valid

DQ[71:0]

I/O Address/Data Bus

ACK(4)

T READ Acknowledge

EOT(4)

T End of Transfer

SSF

T SEARCH Successful Flag

SSV

T

SEARCH Successful Flag

Valid

MULTI_HIT

O Multiple Hit Flag

HIGH_SPEED

I 100MHz Indicator

CLKTUNE[3:0]

I PLL Tuner

SADR[23:0]

CE_L

WE_L

OE_L

ALE_L

LHI[6:0]

LHO[1:0]

BHI[2:0]

BHO[2:0]

FULI[6:0]

FULO[1:0]

FULL

ID[4:0]

VDD

VDDQ

TDI

SRAM Interface

T SRAM Address

T SRAM Chip Enable

T SRAM Write Enable

T SRAM Output Enable

T Address Latch Enable

Cascade Interface

I

Local Hit In

O Local Hit Out

I

Block Hit In

O Block Hit Out

I

Full In

O Full Out

O Full Flag

Device Identification

I

Device Identification

Supplies

Chip Core Supply (1.5V for

n/a 66 and 83MSPS; 1.65 for

100MSPS)

n/a

Chip I/O Supply (2.5 or

3.3V)

Test Access Port

I

Test Access Port’s Test

Data In

TCK

I

Test Access Port’s Test

Clock

TDO

T

Test Access Port’s Test

Data Out

TMS

I

Test Access Port’s Test

Mode Select

TRST_L

I

Test Access Port’s Reset

Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate

See DESCRIPTIONS FOR CONNECTION DIAGRAM (Figure 3, page 9), page 152 for individual connection details.

2. In the previous versions of this specification, this signal was called, “CLK_OUT.”

3. In previous versions of this specification, this signal was called, “PLL_BYPASS.”

4. ACK and EOT Signals require a weak, external pull-down resistor of 47 KΩ or 100 KΩ.

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