M69AW024BE データシートの表示（PDF） - STMicroelectronics

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M69AW024BE

16 Mbit (1M x16) 3V Asynchronous PSRAM

STMicroelectronics 

M69AW024BE

SUMMARY DESCRIPTION

The M69AW024BE is a 16 Mbit (16,777,216 bit)

CMOS memory, organized as 1,024,576 words by

16 bits, and is supplied by a single 2.7V to 3.3V

supply voltage range.

M69AW024BE is a member of STMicroelectronics

PSRAM memory family, based on the one-transis-

tor per-cell architecture. These devices are manu-

factured using dynamic random access memory

cells, to minimize the cell size, and maximize the

amount of memory that can be implemented in a

given area.

However, through the use of internal control logic,

the device is fully static in its operation, requiring

no external clocks or timing strobes, and has a

standard Asynchronous SRAM Interface.

The internal control logic of the M69AW024BE

handles the periodic refresh cycle, automatically,

and without user involvement.

Write cycles can be performed on a single byte by

using Upper Byte Enable (UB) and Lower Byte En-

able (LB).

The device can be put into standby mode using

Chip Enable (E1) or in deep power down mode by

using Chip Enable (E2).

Power-Down mode achieves a very low current

consumption by halting all the internal activities.

Since the refresh circuitry is halted, the duration of

the power-down should be less than the maximum

period for refresh, if the user has not finished with

the data contents of the memory.

Figure 2. Logic Diagram

VCC

20

A0-A19

16

DQ0-DQ15

W

E1

M69AW024BE

E2

G

UB

LB

Table 1. Signal Names

A0-A19

Address Input

DQ0-DQ15 Data Input/Output

E1, E2

Chip Enable, Power Down

G

Output Enable

W

Write Enable

UB

Upper Byte Enable

LB

Lower Byte Enable

VCC

Supply Voltage

VSS

Ground

NC

Not Connected

(no internal connection)

VSS

AI07406b

4/25

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