M69KB096AB80CW8 データシートの表示（PDF） - STMicroelectronics

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M69KB096AB80CW8

64 Mbit (4Mb x 16)/ 104MHz Clock Rate 1.8V Supply - Bare Die Burst PSRAM

STMicroelectronics 

2 Signal descriptions

2 Signal descriptions

M69KB096AB

The signals are summarized in Figure 1: Logic Diagram, and Table 1: Signal Names.

2.1 Address Inputs (A0-A21)

The Address Inputs select the cells in the memory array to access during read and write

operations.

2.2 Data Inputs/Outputs (DQ8-DQ15)

The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected

address during a write or read operation, when Upper Byte Enable (UB) is driven Low. When

disabled, the Data Inputs/Outputs are high impedance.

2.3 Data Inputs/Outputs (DQ0-DQ7)

The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected

address during a write or read operation, when Lower Byte Enable (LB) is driven Low. When

disabled, the Data Inputs/Outputs are high impedance.

2.4 Chip Enable (E)

Chip Enable, E, activates the device when driven Low (asserted). When de-asserted (VIH), the

device is disabled and goes automatically in low-power Standby mode or Deep Power-Down

mode, according to the RCR settings.

2.5 Output Enable (G)

When held Low, VIL, the Output Enable, G, enables the Bus Read operations of the memory.

2.6 Write Enable (W)

Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the

device is in write mode and write operations can be performed either to the configuration

registers or to the memory array.

2.7 Upper Byte Enable (UB)

The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-

DQ15) to or from the upper part of the selected address during a write or read operation.

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