MC80C86 データシートの表示（PDF） - Intel

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MC80C86

16-BIT CHMOS MICROPROCESSOR

Intel 

Symbol

RD

READY

INTR

TEST

NMI

RESET

CLK

VCC

GND

MN MX

M80C86 M80C86-2

Pin No

32

22

18

23

17

21

19

40

1 20

33

Table 1 Pin Description (Continued)

Type

O

Name and Function

READ Read strobe indicates that the processor is performing a

memory of I O read cycle depending on the state of the S2 pin

This signal is used to read devices which reside on the M80C86

local bus RD is active LOW during T2 T3 and TW of any read cycle

and is guaranteed to remain HIGH in T2 until the M80C86 local bus

has floated

This floats to 3-state OFF in ‘‘hold acknowledge ’’

I READY is the acknowledgement from the addressed memory or

I O device that it will complete the data transfer The READY signal

from memory IO is synchronized by the M82C84A Clock Generator

to form READY This signal is active HIGH The M80C86 READY

input is not synchronized Correct operation is not guaranteed if the

setup and hold times are not met

I INTERRUPT REQUEST is a level triggered input which is sampled

during the last clock cycle of each instruction to determine if the

processor should enter into an interrupt acknowledge operation A

subroutine is vectored to via an interrupt vector lookup table

located in system memory It can be internally masked by software

resetting the interrupt enable bit INTR is internally synchronized

This signal is active HIGH

I TEST input is examined by the ‘‘Wait’’ instruction If the TEST input

is LOW execution continues otherwise the processor waits in an

‘‘Idle’’ state This input is synchronized internally during each clock

cycle on the leading edge of CLK

I NON-MASKABLE INTERRUPT an edge triggered input which

causes a type 2 interrupt A subroutine is vectored to via an

interrupt vector lookup table located in system memory NMI is not

maskable internally by software A transition from a LOW to HIGH

initiates the interrupt at the end of the current instruction This input

is internally synchronized

I RESET causes the processor to immediately terminate its present

activity The signal must be active HIGH for at least four clock

cycles It restarts execution as described in the Instruction Set

description when RESET returns LOW RESET is internally

synchronized

I CLOCK provides the basic timing for the processor and bus

controller It is asymmetric with a 33% duty cycle to provide

optimized internal timing

VCC a5V power supply pin

GROUND Both must be connected

I MINIMUM MAXIMUM indicates what mode the processor is to

operate in The two modes are discussed in the following sections

3

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