AS4C256K16E0 データシートの表示（PDF） - Alliance Semiconductor
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AS4C256K16E0 Datasheet PDF : 24 Pages
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AS4C256K16E0
®
Functional description
The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16
bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels.
The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the
512 × 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease
the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:
• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
• Self-refresh cycles*
The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated
testing and insertion equipment. System level features include single power supply of 5V ± 0.5V tolerance and direct interface with TTL logic
families.
Logic block diagram
VCC
GND
COLUMN DECODER
SENSE AMP
DATA
I/O
BUFFER
I/O0 to I/O15
A0
A1
A2
RAS
RAS CLOCK
A3
GENERATOR
A4
A5
A6
A7
UCAS
CAS CLOCK
GENERATOR
A8
LCAS
WE CLOCK
WE
GENERATOR
512×512×16
ARRAY
(4,194,304)
OE
SUBSTRATE
BIAS
GENERATOR
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Symbol
Min
Typ
VCC
4.5
5.0
GND
0.0
0.0
VIH
2.4
–
VIL
–1.0
–
(Ta = 0°C to +70°C)
Max
Unit
5.5
V
0.0
V
VCC + 1
V
0.8
V
*Self-refresh option is available for new generation device only. Contact Alliance for more information.
4/11/01; v.1.1
Alliance Semiconductor
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