AS4C256K16F0-50JC データシートの表示（PDF） - Alliance Semiconductor
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AS4C256K16F0-50JC Datasheet PDF : 25 Pages
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AS4C256K16FO
®
Refresh cycle
Standard
Symbol
Parameter
tCSR CAS setup time (CAS-before-RAS)
tCHR CAS hold time (CAS-before-RAS)
tRPC RAS precharge to CAS hold time
tCPT
CAS precharge time
(CAS-before-RAS counter test)
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
–30
–35
–50
Min Max Min Max Min Max Min Max Unit Notes
10 – 10 – 10 – 10 – ns
3
7
– 7 – 8 – 10 – ns
3
0
– 0 – 0 – 0 – ns
8
– 8 – 8 – 8 – ns
Output enable
Standard
Symbol
Parameter
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
–30
–35
–50
Min Max Min Max Min Max Min Max Unit Notes
tROH RAS hold time referenced to OE
5 – 5 – 5 – 5 – ns
tOEA OE access time
– 8 – 10 – 10 – 10 ns
tOED OE to data delay
5 – 5 – 5 – 8 – ns
tOEZ Output buffer turnoff delay from OE –
6
– 8 – 8–8
ns
8
tOEH OE command hold time
5 – 8 – 8 – 8 – ns
Self refresh cycle
Standard
Symbol
Parameter
(VCC = 5V ± 10%, GND = 0V, Ta = 0° C to +70° C)
–25
–30
–35
–50
Min Max Min Max Min Max Min Max Unit Notes
tRASS RAS pulse width (CBR self refresh) 100K – 100K – 100K – 100K – ns
tRPS RAS precharge time (CBR self refresh) 85 – 85 – 85 – 85 – ns
tCHS CAS hold time (CBR self refresh)
30 – 30 – 30 – 30 – ns
Notes
1 ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.
2 ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
4 AC characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤
VCC.
5 VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the speci-
fied tRCD (max) limit, then access time is controlled exclusively by tCAC.
7 Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the speci-
fied tRAD (max) limit, then access time is controlled exclusively by tAA.
8 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
9 Either tRCH or tRRH must be satisfied for a read cycle.
10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥
tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD
≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If
neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of tCAA or tCAC or tCAP.
14 tASC ≥ tCP to achieve tPC (min) and tCAP (max) values.
15 These parameters are sampled, but not 100% tested.
4/11/01; V.0.9.1
Alliance Semiconductor
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