29F200-120 データシートの表示（PDF） - Alliance Semiconductor

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29F200-120

5V 256K x 8/128K x 8 CMOS Flash EEPROM

Alliance Semiconductor 

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Item

Byte/word

Programming

Chip Erase

Sector Erase

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Description

Programming the AS29F200 is a four bus cycle operation performed on a byte-by-byte or word-

by-word basis.Two unlock write cycles precede the Program Setup command and program data

write cycle. Upon execution of the program command, no additional CPU controls or timings are

necessary. Addresses are latched on the falling edge of CE or WE (whichever is last); data is latched

on the rising edge of CE or WE, (whichever is first). The AS29F200’s automated on-chip program

algorithm provides adequate internally-generated programming pulses and verifies the

programmed cell margin.

Check programming status by sampling data on the DATA polling (DQ7), toggle bit (DQ6), orRY/

BY pin. The AS29F200 returns the equivalent data that was written to it (as opposed to

complemented data), to complete the programming operation.

The AS29F200 ignores commands written during programming. A hardware reset occurring

during programming may corrupt the data at the programmed location.

AS29F200 allows programming in any sequence, across any sector boundary. Changing data from 0

to 1 requires an erase operation. Attempting to program data 0 to 1 results in DQ5 = 1 (exceeded

programming time limits); reading this data after a Read/reset operation returns a 0. When

programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a

reset command returns the device to read mode.

Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional

unlock write cycles; and finally the Chip Erase command.

Chip erase does not require logical 0s written prior to erasure. When the automated on-chip erase

algorithm is invoked with the Chip Erase command sequence, AS29F200 automatically programs

and verifies the entire memory array for an all-zero pattern prior to erase. The AS29F200 returns to

read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time

limit.

Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional

unlock write cycles, and finally the Sector Erase command. Determine the sector to be erased by

addressing any location in the sector. This address is latched on the falling edge of WE; the

command, 30H is latched on the rising edge of WE. The sector erase operation begins after a 80 µs

time-out.

To erase multiple sectors, write the sector erase command to each of the addresses of sectors to

erase after following the six bus cycle operation above. Timing between writes of additional sectors

must be <80 µs, or the AS29F200 ignores the command and erasure begins. During the

time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase

or Erase Suspend) during time-out resets the AS29F200 to read mode, and the device ignores the

sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on

the ignored sectors.

The entire array need not be written with 0s prior to erasure. AS29F200 writes 0s to the entire

sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected

sectors unaffected. AS29F200 requires no CPU control or timing signals during sector erase

operations.

Automatic sector erase begins after erase time-out from the last rising edge of WE from the sector

erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address

must be performed on addresses that fall within the sectors being erased. AS29F200 returns to read

mode after sector erase unless DQ5 is set high by exceeding the time limit.

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