DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

ICPL2630(2000) データシートの表示(PDF) - Isocom

部品番号
コンポーネント説明
メーカー
ICPL2630 Datasheet PDF : 4 Pages
1 2 3 4
SWITCHING SPECIFICATIONS AT TA = 25°C ( VCC = 5V, IF = 7.5mA Unless otherwise noted )
PARAMETER
Propagation Delay Time
to Logic Low at Output
( fig 1 )( note2 )
SYM DEVICE MIN TYP MAX UNITS TEST CONDITION
t
PHL
55 75 ns
R
L
=
350Ω,
C
L
=
15pF
Propagation Delay Time
to Logic High at Output
tPLH
( fig 1 )( note3 )
45 75 ns
RL = 350Ω, CL = 15pF
Common Mode Transient
Immunity at Logic High
CMH ICPL2630
10000
Level Output ( fig 2 )( note7 )
ICPL2631 1000 10000
V/µs
V/µs
IF = 0mA, VCM = 50VPP
RL= 350Ω,VOH= 2Vmin.
Common Mode Transient
Immunity at Logic Low
Level Output ( fig 2 )( note8 )
CM ICPL2630
-10000
L
ICPL2631 -1000 -10000
V/µs
V/µs
V = 50V
CM
PP
RL=350Ω,VOL=0.8Vmax.
NOTES:-
1 Bypassing of the power supply line is required, with a 0.01µF ceramic disc capacitor adjacent to
each isolator. The power supply bus for the isolator(s) should be seperate from the bus for any
active loads. Otherwise a larger value of bypass capacitor (up to 0.1µF) may be needed to supress
regenerative feedback via the power supply.
2 The t propagation delay is measured from the 3.75 mA level Low to High transition of the input
PHL
current pulse to the 1.5V level on the High to Low transition of the output voltage pulse.
3 The tPLH propagation delay is measured from the 3.75mA level High to Low transition of the input
current pulse to the 1.5V level on the Low to High transition of the output voltage pulse.
4 Device considered a two terminal device; pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7
and 8 shorted together.
5 Each channel.
6 Measured between pins 1 and 2 shorted together and pins 3 and 4 shorted together.
7 CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output
will remain in a high logic state (ie Vout > 2.0V).
8 CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output
L
will remain in a low logic state (ie Vout < 0.8V)
IF
0
VO
t
PHL
FIG.1 SWITCHING TEST CIRCUIT
1.5V
t
PLH
5V
1.5V
V
OL
PULSE
GENERATOR
ZO = 50
IF
tr = 5ns
1
2
3
I Monitor
4
F
100
8
5V
7
RL VO
6
5
C = 15pF
L
9/10/00
DB92601-AAS/A1

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]