MACH120-18JI データシートの表示（PDF） - Lattice Semiconductor

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MACH120-18JI

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

FMAX PARAMETERS

The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Be-

cause the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop

designs, fMAX is specified for three types of synchronous designs.

The first type of design is a state machine with feedback signals sent off-chip. This external feedback

could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest

path defining the period is the sum of the clock-to-output time and the input setup time for the exter-

nal signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in

conjunction with an equivalent speed device. This fMAX is designated “fMAX external.”

The second type of design is a single-chip state machine with internal feedback only. In this

case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these condi-

tions, the period is limited by the internal delay from the flip-flop outputs through the internal

feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple in-

ternal counter is a good example of this type of design; therefore, this parameter is sometimes

called “fCNT.”

The third type of design is a simple data path application. In this case, input data is presented

to the flip-flop and clocked through; no feedback is employed. Under these conditions, the pe-

riod is limited by the sum of the data setup time and the data hold time (tS + tH). However, a

lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually,

this minimum clock period determines the period for the third fMAX, designated “fMAX no feed-

back.”

For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this

involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period

will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock

widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is

specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same

path, the overall frequency will be limited by tICS.

All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX

internal is measured directly.

CLK

CLK

LOGIC

REGISTER

(SECOND

CHIP)

LOGIC

REGISTER

tS

tCO

tS

fMAX External 1/(ts + tCO)

CLK

fMAX Internal (fCNT)

CLK

LOGIC

REGISTER

REGISTER

LOGIC

tS

fMAX No Feedback; 1/(ts + tH) or 1/(tWH + tWL)

tSIR

tHIR

fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)

MACH120-12/15

19

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