MACH120-18JI データシートの表示（PDF） - Lattice Semiconductor

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MACH120-18JI

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

BLOCK DIAGRAM

Block A

I/O0–I/O11

12

I/O Cells

12

Macrocells

OE

52 x 54

AND Logic Array

and

Logic Allocator

26

26

52 x 54

AND Logic Array

and

Logic Allocator

OE

Macrocells

12

I/O Cells

12

I/O36–I/O47

Block D

Block B

I/O12–I/O23

12

I/O Cells

12

Macrocells

OE

52 x 54

AND Logic Array

and

Logic Allocator

26

Switch Matrix

I2–I3

I6–I7

4

4

26

52 x 54

AND Logic Array

and

4

Logic Allocator

OE

Macrocells

4

12

I/O Cells

12

I/O24–I/O35

Block C

CLK0/I0, CLK1/I1,

CLK2/I4, CLK3/I5

14129J-1

MACH120-12/15

3

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