MACH4-96 データシートの表示（PDF） - Lattice Semiconductor

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MACH4-96

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

VANTIS

The Macrocell and Output Switch Matrix

Each M4-96/96 PAL block has 16 macrocells, half of which can drive I/O pins; this selection is made by

the output switch matrix. Each macrocell can drive one of four I/O cells. The allowed combinations are

shown in Table 1. Please refer to Figure 7 for macrocell and I/O pin numbers.The macrocells can be

configured as registered, latched, or combinatorial. In combination with the logic allocator, the registered

configuration can be any of the standard flip-flop types. The macrocell provides internal feedback

whether configured with or without the flip-flop, and whether or not the macrocell drives an I/O cell.

The flip-flop clock depends on the mode selected for the macrocell. In synchronous mode, any of

the PAL block clocks generated by the Clock Generator can be used. In asynchronous mode, the

additional choice of either edge of an individual product-term clock is available.

Initialization can be handled as part of a bank of macrocells via the PAL block initialization terms if in

synchronous mode, or individually if in asynchronous mode (Figure 4). In synchronous mode, one of

the PAL block product terms is available each for preset and reset. The swap function determines which

product term drives which function. This allows initialization polarity compatibility with the MACH 1

and 2 series. In asynchronous mode, one product term can be used either to drive reset or preset.

Power-Up

Reset

PAL-Block

Initialization

Product Terms

Common PAL-block resource

Individual macrocell resources

From Logic Allocator

From

PAL-Clock

Generator

Block CLK0

Block CLK1

Block CLK2

Block CLK3

SWAP

AP AR

D/T/L Q

To Output and Input

Switch Matrices

Individual

Initialization

Product Term

Power-Up

Reset

a. Synchronous Mode

From Logic

Allocator

From PAL-Block

Clock Generator

Individual Clock

Product Term

Block CLK0

Block CLK1

AP AR

D/T/L Q

b. Asynchronous Mode

Figure 4. Macrocell

To Output and Input

Switch Matrices

21535A-4

10

MACH4-96/96-15

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