MACH4-96 データシートの表示（PDF） - Lattice Semiconductor

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MACH4-96

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

VANTIS

Figure 2. MACH4-96/96 Input Switch Matrix

21535A-2

The Clock Generator

Each PAL block has a clock generator that can generate four clock signals for use throughout the PAL

block. These four signals are available to all macrocells and I/O cells in the PAL block, whether in

synchronous or asynchronous mode. The clock generator chooses the four signals from the eight

possible signals given by the true and complement versions of the four global clock pin signals.

GCLK0

GCLK1

Block CLK0

(GCLK0 or GCLK1)

Block CLK1

(GCLK1 or GCLK0)

GCLK2

GCLK3

Block CLK2

(GCLK2 or GCLK3)

Block CLK3

(GCLK3 or GCLK2)

Figure 3. PAL Block Clock Generator

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Synchronous and Asynchronous Operation

The MACH 4 family can perform synchronous or asynchronous logic. Each individual cell can be

programmed as synchronous or asynchronous, allowing unlimited “mixing and matching” of the

two logic styles. The selection of synchronous or asynchronous mode affects the logic allocator

and the macrocell, since product terms used for logic in the synchronous mode are used for control

functions in the asynchronous mode.

The Product-Term Array

The M4-96/96 product-term array consists of 80 product terms for logic use, 16 product terms for

output enable use, and two product terms for global PAL block initialization. Each macrocell has

8

MACH4-96/96-15

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