MACH4-96/96-18 データシートの表示（PDF） - Lattice Semiconductor

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MACH4-96/96-18

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

VANTIS

CONNECTION DIAGRAM

Top View

Block A

144-Pin PQFP

Block F

I/O13

1

I/O14

2

I/O15

3

VCC

4

TDI

5

I5

6

GND

7

I0/CLK0

8

I1/CLK1

9

I/O16

10

I/O17

11

VCC

12

I/O18

13

I/O19

14

GND

15

I/O20

16

I/O21

17

I/O22

18

I/O23

19

I/O24

20

I/O25

21

VCC

22

GND

23

I/O26

24

I/O27

25

I/O28

26

I/O29

27

I/O30

28

I/O31

29

GND

30

TMS

31

TCK

32

VCC

I/O32

33

34

I/O33

35

I/O34

36

108

I/O82

107

I/O81

106

I/O80

105

VCC

104

TDO

103

TRST

102

GND

101

I4/CLK3

100

I3/CLK2

99

I/O79

98

97

I/O78

VCC

I/O77

96

95

I/O76

94

GND

93

I/O75

92

I/O74

91

I/O73

90

I/O72

89

I/O71

88

I/O70

87

VCC

86

GND

85

I/O69

84

I/O68

83

I/O67

82

I/O66

81

I/O65

80

I/O64

79

GND

78

I2

77

ENABLE

76

VCC

75

I/O63

74

I/O62

73

I/O61

Block C

PIN DESIGNATIONS

CLK/I

GND

I

I/O

VCC

TDI

= Clock or Input

= Ground

= Input

= Input/Output

= Supply Voltage

= Test Data In

Block D

TMS = Test Mode Select

TCK = Test Clock

TDO = Test Data Out

TRST = Test Reset

ENABLE = Program

4

MACH4-96/96-15

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