MACH445-12YC データシートの表示（PDF） - Lattice Semiconductor
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MACH445-12YC Datasheet PDF : 28 Pages
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Parameter
Symbol
Parameter Description
-12
Min Max
tICS
Input Register Clock to Output Register Setup
D-type 9
T-type 10
tWICL
tWICH
fMAXIR
tIGO
tIGOL
Input Register Clock Width
Maximum Input Register Frequency 1/(t WICL + tWICH)
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
LOW
6
HIGH
6
83.3
16
18
tIGSA
Input Latch Gate to Output Latch Setup Using
4
Product Term Output Latch Gate
tIGSS
Input Latch Gate to Output Latch Setup Using Global
9
Output Latch Gate
tWIGL
tAR
tARW
tARR
tAP
tAPW
tAPR
tEA
tER
Input Latch Gate Width LOW
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 2)
Asynchronous Reset Recovery Time (Note 2)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 2)
Asynchronous Preset Recovery Time (Note 2)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
6
16
12
10
16
12
8
2
12
2
12
Input Register with Standard-Hold-Time Option
tPDL
Input, I/O, or Feedback to Output Through
14
Transparent Input Latch
tSIR
Input Register Setup Time
2
tHIR
Input Register Hold Time
3
tSIL
Input Latch Setup Time
2
tHIL
Input Latch Hold Time
3
tSLLA
Setup Time from Input, I/O, or Feedback Through
4
Transparent Input Latch to Product Term Output Gate
tSLLS
Setup Time from Input, I/O, or Feedback Through
9
Transparent Input Latch to Output Gate
tPDLL
Input, I/O, or Feedback to Output Through Transparent
16
Input and Output Latches
Unit
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MACH445-12 (Com’l)
11
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