MACH445-15 データシートの表示（PDF） - Lattice Semiconductor

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MACH445-15

High-Density EE CMOS Programmable Logic

Lattice Semiconductor 

CONNECTION DIAGRAM MACH445 (MACH435)

Top View

BLOCK A

PQFP

BLOCK H

GND

GND

TDI

I5

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I0/CLK0

VCC

VCC

GND

GND

I1/CLK1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

TMS

TCK

GND

GND

1

2

3

4 (83)

5 (12)

6 (13)

7 (14)

8 (15)

9 (16)

10 (17)

11 (18)

12 (19)

13 (20)

14

15

16

17

18 (23)

19 (24)

20 (25)

21 (26)

22 (27)

23 (28)

24 (29)

25 (30)

26 (31)

27

28

29

30

80

79

78

77

(73) 76

(72) 75

(71) 74

(70) 73

(69) 72

(68) 71

(67) 70

(66) 69

(65) 68

67

66

65

64

(62) 63

(61) 62

(60) 61

(59) 60

(58) 59

(57) 58

(56) 57

(55) 56

(54) 55

(41) 54

53

52

51

GND

GND

TD0

TRST*

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

I4/CLK3

GND

GND

VCC

VCC

I3/CLK2

I/O47

I/O46

I/O45

I/O44

I/O43

I/O42

I/O41

I/O40

I2

ENABLE*

GND

GND

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

BLOCK D

BLOCK E

17468E-2

MACH445-12/15/20

3

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