MACH211SP-10 データシートの表示（PDF） - Unspecified

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MACH211SP-10

High-Performance EE CMOS In-System Programmable Logic

Unspecified 

VANTIS

FUNCTIONAL DESCRIPTION

The MACH211SP consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins

feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design

implementation. There are two clock pins that can also be used as dedicated inputs.

The PAL Blocks

Each PAL block in the MACH211SP (Figure 1) contains a 64-product-term logic array, a logic

allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each

PAL block with 26 inputs. This makes the PAL block look effectively like an independent

“PALCE26V16” with 8 buried macrocells.

In addition to the logic product terms, two output enable product terms, an asynchronous reset

product term, and an asynchronous preset product term are provided. One of the two output

enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the

PAL block are initialized together.

The Switch Matrix

The MACH211SP switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each

PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix

distributes these signals back to the PAL blocks in an efficient manner that also provides for high

performance. The design software automatically configures the switch matrix when fitting a design

into the device.

The Product-term Array

The MACH211SP product-term array consists of 64 product terms for logic use, and 4

special-purpose product terms. Two of the special-purpose product terms provide programmable

output enable; one provides asynchronous reset, and one provides asynchronous preset.

The Logic Allocator

The logic allocator in the MACH211SP takes the 64 logic product terms and allocates them to the

16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design

software automatically configures the logic allocator when fitting the design into the device.

Table 1 illustrates which product term clusters are available to each macrocell within a PAL block.

Refer to Figure 1 for cluster and macrocell numbers.

Table 1. Logic Allocation

Macrocell

Output

Buried

Available

Clusters

Macrocell

Output

Buried

Available

Clusters

M0

C0, C1, C2

M8

C7, C8, C9, C10

M1

C0, C1, C2, C3

M9

C8, C9, C10, C11

M2

C1, C2, C3, C4

M10

C9, C10, C11, C12

M3

C2, C3, C4, C5

M11

C10, C11, C12, C13

M4

C3, C4, C5, C6

M12

C11, C12, C13, C14

M5

C4, C5, C6, C7

M13

C12, C13, C14, C15

M6

C5, C6, C7, C8

M14

C13, C14, C15

M7

C6, C7, C8, C9

M15

C14, C15

8

MACH211SP-7/10/12/15

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