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MACH220-10JC データシートの表示(PDF) - Advanced Micro Devices

部品番号
コンポーネント説明
メーカー
MACH220-10JC
AMD
Advanced Micro Devices AMD
MACH220-10JC Datasheet PDF : 33 Pages
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CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
VIN = 2.0 V VCC = 5.0 V, TA = 25°C,
VOUT= 2.0 V f = 1 MHz
AMD
Typ Unit
6
pF
8
pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter
Symbol Parameter Description
tPD Input, I/O, or Feedback to Combinatorial Output (Note 3)
D-type
tS
Setup Time from Input, I/O, or Feedback to Clock
T-type
tH
Register Data Hold Time
tCO Clock to Output (Note 3)
tWL
Clock Width
tWH
LOW
HIGH
D-type
External Feedback 1/(tS + tCO)
Maximum
T-type
fMAX
Frequency
(Note 1)
Internal Feedback (fCNT)
D-type
T-type
No Feedback
1/(tWL + tWH)
tSL Setup Time from Input, I/O, or Feedback to Gate
tHL Latch Data Hold Time
tGO Gate to Output (Note 3)
tGWL Gate Width LOW
tPDL Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
-14
Min Max
14.5
8.5
10
0
10
7.5
7.5
53
50
61.5
57
66.5
8.5
0
12
7.5
17
-18
Min Max
18
12
13.5
0
12
7.5
7.5
40
38
53
44
66.5
12
0
13.5
7.5
20.5
-24
Min Max Unit
24 ns
16
ns
17
ns
0
ns
14.5 ns
10
ns
10
ns
32
MHz
30.5
MHz
38
MHz
34.5
MHz
50
MHz
16
ns
0
ns
14.5 ns
10
ns
26.5 ns
tSIR
tHIR
tICO
tICS
tWICL
tWICH
fMAXIR
tSIL
tHIL
tIGO
tIGOL
Input Register Setup Time
Input Register Hold Time
Input Register Clock to Combinatorial Output
Input Register Clock to Output Register Setup
D-type
T-type
Input Register Clock Width
Maximum Input Register Frequency
LOW
HIGH
1/(tWICL+ tWICH)
Input Latch Setup Time
Input Latch Hold Time
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
2.5
2.5
2.5
ns
3
3.5
4
ns
18
22
28 ns
14.5
18
24
ns
16
19.5
25.5
ns
7.5
7.5
10
ns
7.5
7.5
10
ns
66.5
66.5
50
MHz
2.5
2.5
2.5
ns
3
3.5
4
ns
20.5
24
30 ns
23
26.5
32.5 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
11
14.5
18
ns
tIGS
tWIGL
tPDLL
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
16
19.5
25.5
ns
7.5
7.5
10
ns
19.5
23
29 ns
MACH220-14/18/24 (Ind)
15

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