MAX1213N データシートの表示（PDF） - Maxim Integrated
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MAX1213N Datasheet PDF : 21 Pages
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1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential RL = 100Ω. Limits are for TA = -40°C to +85°C, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low
VIL
Digital Input-Voltage High
VIH
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
tPDL
Figure 5
CLK-to-DCLK Propagation Delay
tCPDL Figure 5
DCLK-to-Data Propagation Delay tCPDL - tPDL Figure 5 (Note 3)
LVDS Output Rise Time
LVDS Output Fall Time
tRISE
tFALL
20% to 80%, CL = 5pF
20% to 80%, CL = 5pF
Output Data Pipeline Delay
tLATENCY Figure 5
MIN TYP MAX UNITS
0.2 x AVCC V
0.8 x AVCC
V
1.98
ns
4.58
ns
2.30 2.56 2.82
ns
450
ps
450
ps
11
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
Digital Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
(Note 4)
AVCC
OVCC
IAVCC
IOVCC
PDISS
PSRR
fIN = 100MHz
fIN = 100MHz
fIN = 100MHz
Offset
Gain
1.70 1.80 1.90
V
1.70 1.80 1.90
V
337
366
mA
63
69
mA
720
783
mW
1.8
mV/V
1.5
%FS/V
Note 1: Values at TA ≥ +25°C guaranteed by production test, values at TA < +25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are computed from an end-point curve fit.
Note 3: Parameter guaranteed by design and characterization: TA = -40°C to +85°C.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
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