MAX1450 データシートの表示（PDF） - Maxim Integrated
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MAX1450 Datasheet PDF : 12 Pages
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Low-Cost, 1%-Accurate Signal Conditioner
for Piezoresistive Sensors
PIN
1
2, 3,
12, 16
4
5
6
7
8
9
10
11
13
14
15
17
18
19
20
NAME
INP
I.C.
SOTC
SOFF
A1
A0
OFFTC
OFFSET
BBUF
FSOTRIM
A2
OUT
VDD
ISRC
BDRIVE
VSS
INM
Pin Description
FUNCTION
Positive Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.
Internally connected. Leave unconnected.
Offset TC Sign Bit Input. A logic low inverts VOFFTC with respect to VSS. This pin is internally pulled to VSS
via a 1MΩ (typical) resistor. Connect to VDD to add VOFFTC to the PGA output, or leave unconnected (or
connect to VSS) to subtract VOFFTC from the PGA output.
Offset Sign Bit Input. A logic low inverts VOFFSET with respect to VSS. This pin is internally pulled to VSS via
a 1MΩ (typical) resistor. Connect to VDD to add VOFFSET to the PGA output, or leave unconnected (or con-
nect to VSS) to subtract VOFFSET from the PGA output.
PGA Gain-Set Input. Internally pulled to VSS via a 1MΩ (typical) resistor. Connect to VDD for a logic high or
VSS for a logic low.
PGA Gain-Set LSB Input. Internally pulled to VSS via a 1MΩ (typical) resistor. Connect to VDD for a logic
high or VSS for a logic low.
Offset TC Adjust. Analog input summed with PGA output and VOFFSET. Input impedance is typically 1MΩ.
Rail-to-rail input range.
Offset Adjust Input. Analog input summed with PGA output and VOFFTC. Input impedance is typically
1MΩ. Rail-to-rail input range.
Buffered Bridge-Voltage Output (the voltage at BDRIVE). Use with correction resistor RSTC to correct for FSO
tempco.
Bridge Drive Current-Set Input. The voltage on this pin sets the nominal IISRC. See the Bridge Drive section.
PGA Gain-Set MSB Input. Internally pulled to VSS via a 11kΩ (typical) resistor. Connect to VDD for a logic
high or VSS for a logic low.
PGA Output Voltage. Connect a 0.1µF capacitor from OUT to VSS.
Positive Supply Voltage Input. Connect a 0.1µF capacitor from VDD to VSS.
Current-Source Reference. Connect a 50kΩ (typical) resistor from ISRC to VSS.
Sensor Excitation Current Output. This pin drives a nominal 0.5mA through the bridge.
Negative Power-Supply Input.
Negative Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.
______________ Detailed Description
Analog Signal Path
The MAX1450’s signal path is fully differential and com-
bines the following three stages: a 3-bit PGA with
selectable gains of 39, 65, 91, 117, 143, 169, 195, and
221; a summing junction; and a differential to single-
ended output buffer (Figure 1).
Programmable-Gain Amplifier
The analog signal is first fed into a programmable-gain
instrumentation amplifier with a CMRR of 90dB and a
common-mode input range from VSS to VDD. Pins A0,
A1, and A2 set the PGA gain anywhere from 39V/V to
221V/V (in steps of 26).
A2 A1 A0
INP
PGA
INM
OFFTC SOTC
±
Σ
OUT
A=1
±
OFFSET SOFF
Figure 1. Signal-Path Functional Diagram
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