MAX1458 データシートの表示（PDF） - Maxim Integrated
部品番号
コンポーネント説明
メーカー
MAX1458 Datasheet PDF : 19 Pages
| |||
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Table 1. Input-Referred Offset DAC
Correction Values
IRO DAC
OFFSET OFFSET
CORREC- CORREC-
TION
TION AT
VALUE
SIGN
C2
C1
C0
% of VDD
(%)
VDD =
(Mv)
+7
1
111
+1.25
+63
+6
1
110
+1.08
+54
+5
1
101
+0.90
+45
+4
1
100
+0.72
+36
+3
1
011
+0.54
+27
+2
1
010
+0.36
+18
+1
1
001
+0.18
+9
+0
1
000
0
0
-0
0
000
0
0
-1
0
001
-0.18
-9
-2
0
010
-0.36
-18
-3
0
011
-0.54
-27
-4
0
100
-0.72
-36
-5
0
101
-0.90
-45
-6
0
110
-1.08
-54
-7
0
111
-1.25
-63
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor CMOS
technology and contains eight selectable gain levels from
41 to 230, in increments of 27 (Table 2). The output of
the PGA is fed to the output summing junction. The three
PGA gain bits A2, A1, and A0 are stored in the configura-
tion register.
Output Summing Junction
The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the offset
TC correction voltages are gained by a factor of 2.3 before
being fed into the summing junction, increasing the offset
and offset TC correction range. The offset sign bit and off-
set TC sign bit are stored in the configuration register. The
offset sign bit determines if the offset correction voltage is
added to (sign bit is high) or subtracted from (sign bit is low)
the PGA output. Negative offset TC errors require a logic
high for the offset TC sign bit. Alternately, positive offset
TC errors dictate a logic low for the offset TC sign bit. The
output of the summing junction is fed to the output buffer.
Table 2. PGA Gain Settings and IRO DAC
Step Size
PGA
VALUE
PGA
GAIN
(V/V)
0
000
41
1
001
68
2
010
95
3
0 1 1 122
4
1 0 0 149
5
1 0 1 176
6
1 1 0 203
7
1 1 1 230
OUTPUT-
REFERRED IRO
DAC STEP SIZE
(VDD = 5V) (V)
0.369
0.612
0.855
1.098
1.341
1.584
1.827
2.070
Output Buffer
OUT can drive 0.1μF of capacitance. If CS is brought low,
OUT becomes high impedance (resulting in typical output
impedance of 1MΩ). The output is current limited and can
be shorted to either VDD or VSS indefinitely.
The maximum output voltage can be limited using the
LIMIT pin. Output limiting can be performed for sensor
diagnostic purposes. Connect LIMIT to VDD to disable the
voltage-limiting feature.
Bridge Drive
Fine FSO correction is accomplished by varying the sen-
sor excitation current with the 12-bit FSO DAC (Figure 3).
Sensor bridge excitation is performed by a programmable
current source capable of delivering up to 2mA. The refer-
ence current at ISRC is established by resistor RISRC and
by the voltage at node ISRC (controlled by the FSO DAC).
The reference current flowing through this pin is multiplied
by a current mirror (AA ≅ 14) and then made available at
BDRIVE for sensor excitation. Modulation of this current
with respect to temperature can be used to correct FSOTC
errors, while modulation with respect to the output voltage
(VOUT) can be used to correct FSO linearity errors.
Digital-to-Analog Converters
The four 12-bit, sigma-delta DACs typically settle in less
than 100ms. The four DACs have a corresponding memory
register in EEPROM for storage of correction coefficients.
Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from VDD and controls VISRC
which, in conjunction with RISRC, sets the baseline sen-
sor excitation current. The Offset DAC also takes its refer-
ence from VDD and provides a 1.22mV resolution with a
www.maximintegrated.com
Maxim Integrated │ 6
Share Link: 